FPGA validated RISC V system on chip with a custom systolic array accelerator for edge AI inference
TL;DR
A complete FPGA-validated RISC-V SoC in which a five-stage RV32IM processor works alongside a custom systolic MAC array, and two propositions are formally proved that the output-stationary schedule reduces computation cycles by a naïve, unblocked sequential CPU execution.
Abstract
Running deep-learning inference on constrained edge hardware calls for architectures that cut both latency and memory traffic at once—not one at the expense of the other. This paper describes a complete FPGA-validated RISC-V SoC in which a five-stage RV32IM processor works alongside a custom \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$4{\times }4$$\end{document} output-stationary systolic MAC array. An AXI4 crossbar ties the two parts together, and a scatter–gather DMA engine moves operand tiles and results so the processor stays free for control work during inference. Rather than adding custom opcodes, the accelerator is exposed through memory-mapped registers, which means existing RISC-V toolchains need no modification at all. The target device is the Xilinx Artix-7 XC7A35T on a Digilent Basys 3 board. Both Vivado XSim simulation and on-board runs confirm that a \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$4{\times }4$$\end{document} matrix multiply finishes in 320 ns at 100 MHz, giving a compute-phase throughput of 1.16 GOPS. The systolic compute phase completes in \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$3N{-}1 = 11$$\end{document} cycles (110 ns); the full end-to-end tile latency including AXI handshaking is 320 ns. After place-and-route the design uses 39.5% LUTs (8214 of 20,800), 17.8% DSP48E1 slices (16 of 90), and 16.0% BRAM (8 of 50) on the XC7A35T, with a total on-chip power of 148 mW and a compute-phase efficiency of 7.86 GOPS/W. The processing elements natively operate on INT8 quantised inputs sign-extended to 18 bits to match the DSP48E1’s narrower multiplier port, with 64-bit accumulators preventing overflow across a full tile. Two propositions are formally proved: the first establishes that the output-stationary schedule reduces computation cycles by \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\Theta (N^{2}/3)$$\end{document} relative to a naïve, unblocked sequential CPU execution, and the second shows a factor-N reduction in weight-memory reads under the same naïve baseline assumption. The design is validated for functional correctness on physical silicon; power, DMA-overlap, and sustained-throughput figures are estimates derived from Vivado post-implementation analysis and the analytical performance model rather than direct on-board measurement. Among open RISC-V accelerator designs the proposed SoC stands out by combining plain Verilog source, operation on the lower-cost Artix-7 without any embedded ARM host, memory-mapped control that keeps the compiler unmodified, DMA-driven transfers, and a closed-form performance model that matches the measured numbers.