Jul 2026· 2026 International Conference on Electronics, Computing, Communication and Control Technology (ICECCC)· pp. 1-6· 0 citations· 15 references
Abstract
Most general purpose processors were never built for the kind of dense arithmetic that neural network inference demands, and running such workloads on a CPU tends to burn power on memory traffic and instruction overhead rather than useful computation. This paper describes a compact neural processing unit (NPU) built to sit alongside a RISC-V core inside a resource-limited SoC. At its core is an 8 × 8 weightstationary systolic array capable of 64 multiply-accumulate (MAC) operations per clock cycle, fed by a four-state DMA controller that moves matrix tiles into two on-chip SRAM buffers without CPU involvement, so the array rarely stalls waiting on data. The RTL was verified in Verilator with cycle-accurate simulation, then carried through Cadence Genus synthesis on a SCL 180 nm standard cell library. The result is a 500 MHz design occupying about $58,236 \mu \mathrm{m}^{2}$ of silicon and reaching a measured peak of $32 \text{GMAC} / \mathrm{s}$ - figures that we believe justify this class of accelerator for tightly area-constrained edge deployments.
Edge-AI systems for fluorescence spectrum classification require low-latency inference and efficient hardware integration to support real-time environmental monitoring. This paper presents the design and implementation of a RISC-V based system-on-chip (SoC) with a memorymapped neural network accelerator (NNA) on Caravel. The proposed architecture employs a softcore RISC-V processor to control a fixed-point feedforward neural network accelerator through a Wishbone/MMIO interface, enabling modular integration without modifying the processor pipeline. The accelerator performs multiply-accumulate, activation, and argmax-based classification using quantized parameters stored in hardware-compatible memory files. Design verification is carried out through RTL simulation and Caravel-oriented MMIO validation, including register write, inference triggering, and readback of status, output class, and cycle count. Simulation results show 50 passing samples with zero mismatch and an inference latency of 21 clock cycles. The design is also evaluated using the OpenLane ASIC flow, which produces hardened macro outputs and wrapper-level integration, demonstrating physical implementability. The proposed system provides a practical and scalable approach for integrating dedicated neural network hardware into an open RISC-V SoC platform.
Farsya Ra'isah Fadhilia, T. Mujiono, A. N. Irfansyah· International Seminar on Int...· 0 citations
The rise in edge computing, and domain-specific workloads, necessitates the development of hardware acceleration with increased flexibility and lower latency that will be tightly coupled to open-source processor cores. In this paper, we explore the design and bare-metal implementation of a RISC-V SoC comprising a PicoRV32 scalar core and two memory-mapped hardware accelerators: FPSQRT core and a reconfigurable CRC-32 integrity engine. Using a customized three-state AXI4-Lite FSM-based interface, our design effectively separates the acceleration compute latency from that of the bus timings enabling bare-metal firmware to perform its coprocessor computations without OS intervention. Simulation results show performance speed-ups of 1.96x and 9x for the FPSQRT and CRC-32 respectively giving a total speedup of 12x relative to software only. Post-implementation synthesis on the Xilinx Zynq-7000 family FPGA (XC7Z020) shows full timing closure at a clock frequency of 100 MHz with WNS of +7.058 ns. Resource utilization figures are exceptionally low with the design requiring only 5,208 Slice LUT (9.8%), and 11.4% of block RAM with total on-chip power dissipation of 1.694 W. Our hardware-in-the-loop test on the Digilent ZedBoard confirmed the functional accuracy and operational stability with bare-metal operation status confirmed by LED (T21, T22) and a serial console.
P.anuradha, Vulapala Tejashwi, Meenugu Venkateshwarlu et al.· 2026 7th International Confe...· 0 citations
The fast advancement of deep neural networks has led to the escalation of hardware accelerator needs that achieve high functionality as they comply with strict requirements of power and latency, particularly in edge and embedded artificial intelligence. In this paper, the research introduce a low power, pipelined single-precision (32 bits) floating-point data path that is to be used in neural network accelerators compliant with the IEEE 754 single-precision standard. The suggested design uses multi-stage pipelining on addition, multiplication and accumulation units, which greatly decreases the critical path delays and enhances the overall throughput. Efficiency of power is also by ensuring that its techniques such as operand isolation, clock-conscious staging of pipelines and minimized switching activity in arithmetic units. The architecture has a combined optimization in latency, energy, and numerical accuracy, making it possible to infer the numerical accuracy of resource-constrained platforms in real-time. Simulations after synthesis show that the proposed data path has significant propagation delay and dynamic power improvements over the state-of-the-art non-pipelined floating-point implementations and can compute the accuracy needed by the deep learning workloads. Its scalable and modular design is flexible and can be easily adapted to other neural network designs. The findings demonstrate the strength of the targeted design towards addressing the increasing demand of high-performance, low-energy neural network hardware, which provides a viable approach to edge AI systems with severe demands on both power and performance.
K. Kalaichelvi, M. Deepika, M. Bhuvaneshwari et al.· International Conference Com...· 0 citations
The results indicate that exploiting the inherent parallelism of analog computation offers a promising pathway toward ultra-low-power AI inference, making the proposed architecture a potential alternative for energy-constrained edge applications.
Andrei Iliescu, O. N. Ionescu, Adrian Iosif· Electronics· 0 citations
When executing common Neural Networks (NNs) on custom AI accelerators, the high performance suggested by advertised Giga or Tera Operations per Second (GOPS/TOPS) is typically not achieved, as low hardware utilization often leads to an effective performance in the single-digit percentage range of the theoretical peak. This discrepancy arises as NNs are typically designed without accounting for the target hardware, leading to inefficient mappings and software optimizations that fail to deliver the expected gains. Addressing this, we present a hardware-aware workflow that combines accurate latency modeling and design space exploration to optimize both neural network architectures and the underlying systolic-array-based accelerator. We develop and validate two high-precision latency models for two different Row-Stationary (RS) dataflows on our target accelerator. Using these models together with a structured search space generation, we generate Pareto-optimal search spaces in terms of achieved GOPS and latency for a given hardware target, and use these for a Bayesian Bayesian Hardware-Aware Neural Architecture Search. We further explore the accelerator design itself in a subsequent hardware DSE stage, varying the PE array dimensions and clock ratio to identify hardware configurations that maximize efficiency and minimize inference latency for each network and dataflow. We demonstrate our approach on ResNet-like networks. On the original hardware, the discovered ResNet-50-like architecture achieves an 85% relative increase in hardware utilization, reduces latency by 21% and parameter count by 18%, and maintains baseline ImageNet accuracy. On the optimized hardware, latency and area are further reduced while efficiency is increased by up to 94%, with up to 20% fewer PEs compared to the baseline configuration. For ResNet-34, similar trends are observed, with latency reductions exceeding 33% and efficiency gains up to 43%. To enable reproducibility, we open-source our complete workflow of latency models, search space generation, NAS and training pipeline.
Annina Gutermann, Alexey Serdyuk, Foivos Paraskevas et al.· Journal of Signal Processing...· 0 citations
Large language models (LLMs) place unprecedented and still-growing demands on the hardware that trains and serves them. This review surveys the full landscape of AI hardware accelerators for LLMs, including general-purpose GPUs, custom ASICs such as TPUs, Trainium, Groq, and Cerebras, reconfigurable FPGAs, processing-in-memory and near-memory architectures, and emerging neuromorphic and photonic approaches across cloud and edge deployment. Using the transformer's computational structure and roofline analysis as a common framework, we show that the decisive constraint on LLM acceleration is not arithmetic but memory: the autoregressive decode phase is bandwidth-bound, the key-value cache can rival the model weights in size, and data movement dominates energy. Comparing platforms on compute, memory, energy, programmability, and scalability, we find that no single architecture is optimal across workloads: GPUs remain the flexible default and the workhorse of training; domain-specific ASICs win at scale for stable, high-volume workloads; processing-in-memory is the most promising near-term response to the memory wall, entering systems as a heterogeneous complement; and neuromorphic and photonic computing, while promising, are not yet production-ready at frontier scale. Future progress depends on hardware-algorithm co-design and heterogeneous, memory-centric systems: for large language models, the memory system has become the computer.
Siddharth Patel, Rohit Singh· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.
