Skip to content
Log in

Author

V. Kiran

View on Semantic Scholar

1 paper indexed here

We haven’t gathered this author’s papers yet. Follow them and we’ll fetch their work.

Not the right person? Other researchers publish under this name.

#edge computing Open access Aug 2026

FPGA validated RISC V system on chip with a custom systolic array accelerator for edge AI inference

A complete FPGA-validated RISC-V SoC in which a five-stage RV32IM processor works alongside a custom systolic MAC array, and two propositions are formally proved that the output-stationary schedule reduces computation cycles by a naïve, unblocked sequential CPU execution.

Srujan Sateesh Kalagi, K. R. V. Kumar, Shashank Dharamshetty et al. · 0 citations