Jul 2026· 2026 7th International Conference on Smart Systems and Inventive Technology (ICSSIT)· pp. 192-198· 0 citations· 21 references
Abstract
The rise in edge computing, and domain-specific workloads, necessitates the development of hardware acceleration with increased flexibility and lower latency that will be tightly coupled to open-source processor cores. In this paper, we explore the design and bare-metal implementation of a RISC-V SoC comprising a PicoRV32 scalar core and two memory-mapped hardware accelerators: FPSQRT core and a reconfigurable CRC-32 integrity engine. Using a customized three-state AXI4-Lite FSM-based interface, our design effectively separates the acceleration compute latency from that of the bus timings enabling bare-metal firmware to perform its coprocessor computations without OS intervention. Simulation results show performance speed-ups of 1.96x and 9x for the FPSQRT and CRC-32 respectively giving a total speedup of 12x relative to software only. Post-implementation synthesis on the Xilinx Zynq-7000 family FPGA (XC7Z020) shows full timing closure at a clock frequency of 100 MHz with WNS of +7.058 ns. Resource utilization figures are exceptionally low with the design requiring only 5,208 Slice LUT (9.8%), and 11.4% of block RAM with total on-chip power dissipation of 1.694 W. Our hardware-in-the-loop test on the Digilent ZedBoard confirmed the functional accuracy and operational stability with bare-metal operation status confirmed by LED (T21, T22) and a serial console.
A systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted.
Omar Hernandez-Yañez, A. Juárez-Lora, J. Y. Montiel-Pérez et al.· Electronics· 0 citations
The paper describes the architecture, implementation, and testing of a lightweight 32-bit RISC-V processor equipped with a MAC and single-layer perceptron accelerators. In this work, a simple approach to integrate acceleration components using the classic five-stage pipeline structure (IF, ID, EX, MEM, WB) without any change in the instruction set was proposed, resulting in minimal integration overhead. The architecture was implemented using synthesizable Verilog HDL, and the implementation was done using Xilinx Artix-7 FPGA board with Vivado tool for simulation, synthesis, implementation, and bitstream generation process. From the post-implementation results, it can be seen that timing closure was achieved with operating frequency of 100 MHz, worst negative slack (WNS) of +0.741 ns, and worst hold slack (WHS) of +0.148 ns. The system consumed 3.6% of logic utilization in terms of LUTs and 10% of DSP slice utilization; in addition, total power consumed on chip by the system was estimated to be 0.071 W. Hardware functional correctness was demonstrated using FPGA hardware execution where the result obtained by the system was observed using LED and LCD interface.
Vivek Raju Kosigi, B. C. Marepally· 2026 7th International Confe...· 0 citations
With the rise in popularity of applications requiring high-performance arithmetic acceleration, there’s an increasing need for architectural enhancements to low-power embedded and signal processor cores. This paper discusses the design and hardware implementation of an application-specific Multiply-Accumulate (MAC) instruction developed for the open-source PicoRV32 RISC-V processor using the Pico Co-Processor Interface (PCPI). A new opcode-based decode mechanism will enable this process, where a specific field will be checked in the instruction to activate the MAC operation, without having to change the underlying RISC-V ISA. Register-to-register execution will be possible in this hardware MAC-based architecture because it will allow for two-operand forwarding from the processor register file to the hardware MAC unit and back through the PCPI for write-back. The design has been implemented in Verilog and verified through functional simulation and FPGA synthesis by using Vivado. Synthesis results indicate that the MAC-enabled processor utilizes an area-efficient design, where 1,338 LUTs, 953 flip-flops, 2 DSP slices, and very little BRAM were used. Performance metrics show that significant reductions in execution cycles were achieved from the MAC-enabled processor versus a baseline RISC-V processor and therefore validates the efficacy of the proposed custom instruction for compute-intensive workloads
S. Hemajothi, S. Jalaja, M. Kishore et al.· International Conference on...· 0 citations
This paper describes NexusV, a small, ultra-low-power, 32-bit RV32I+ZiCSR RISC-V softcore microcontroller optimized for resource-constrained embedded systems. The processor employs a deterministic multi-cycle design that timemultiplexes a single Arithmetic Logic Unit (ALU) to minimize datapath logic. Synthesized on the PYNQ-Z2 FPGA board, the core operates at a maximum frequency of 90 MHz, achieving a performance of 0.18 DMIPS/MHz while utilizing only 1,134 LUTs and 406 Flip-Flops. The entire system consumes a highly competitive dynamic power of 18 mW and features a full software ecosystem capable of running C code via the standard RISC-V GCC toolchain. Operational integrity was verified through physical hardware testing and the Dhrystone benchmark alongside integrated AMBA APB3 UART, SPI, and PWM peripherals. These features make NexusV a viable Intellectual Property (IP) core for low-power control units in battery-powered devices.
Prithiviraj Rajalingam, Sudeshna Shettygari, S. S. et al.· 2026 International Conferenc...· 0 citations
To satisfy the low-overhead and high-throughput requirements of embedded computing platforms executing cryptographic workloads, this study presents a high-performance RISC-V CPU IP core compatible with the standard RV32IM architecture. Instead of introducing dedicated cryptographic instructions, the proposed design enhances the execution efficiency of algorithms such as SM3 and SM4 through microarchitectural optimization of arithmetic units. A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput, while an enhanced radix-4 SRT divider incorporating leading-zero detection, result caching, and dynamic iteration control is proposed to reduce division latency. All modules are implemented in Verilog and integrated into a five-stage RISC-V pipeline. Functional verification is performed using a complete RVM instruction test suite, followed by FPGA-based performance evaluation. Experimental results demonstrate that the multiplier generates 64-bit results within a single clock cycle in 32-bit scenarios, reducing latency by more than 70% compared with conventional Wallace-tree implementations. The proposed architecture provides an efficient computing platform for secure embedded systems and offers implementation references for real-time signal processing, communication security, and electromagnetic information systems.
This paper describes DeepSig's CUDA-based acceleration backend for the OCUDU physical layer and O-RAN fronthaul path, integrated through acceleration interfaces that are largely independent of the underlying acceleration mechanism. The design accelerates PDSCH, PUSCH, SRS, PRACH, split-8 lower-PHY transforms, and O-RAN fronthaul (O-FH) IQ compression/decompression while preserving existing factories, resource-grid interfaces, PRACH-buffer interfaces, and channel processors. CUDA-visible grids, device-side softbit buffers, stream events, pinned staging buffers, and managed-memory policies keep data resident on the accelerator when the platform and radio split permit it. On an NVIDIA DGX Spark platform with a GB10 GPU and ARM CPU host, representative measurements with CPU baselines pinned to high-capacity cores show up to 10.3x PUSCH speedup, 2.7x PDSCH speedup, 19.7x split-8 low-PHY RX speedup with slot-shaped batching and scattered mapped zero-copy, 91.4x O-FH BFP12 decompression speedup, and 28.8x PRACH detector speedup against the production CPU path, with CPU and GPU 10% BLER thresholds agreeing to within 0.064 dB in the tested PUSCH sweeps. The same resident pipeline provides an execution substrate for AI-RAN, allowing machine-learned channel estimation, neural receivers, and AI-native air-interface research to run beside standards-compliant baseband kernels.
M. Pennybacker, Wanze Liu, A. Kharchenko et al.· 2 citations
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