Low-power analog integrated implementation of the learning vector quantization algorithm for interdisciplinary applications
TL;DR
A new, energy-efficient, fully analog integrated architecture of the Learning Vector Quantization algorithm, utilizing a 90nm CMOS process, employing the Cadence IC Suite for both the schematic and physical design stages.
Abstract
This study introduces a new, energy-efficient, fully analog integrated architecture of the Learning Vector Quantization algorithm. The design showcases its adeptness in effectively managing multiple input features, ensuring high precision, and minimizing power consumption. The main components of the algorithm are Gaussian function and argmax operator circuits. The operational concepts of the architecture are elaborated in detail and are applied to a power-efficient (\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.28 \mu W$$\end{document}) configuration with a low voltage (0.6V) setup. This implementation is tailored for two distinct classification tasks: digit recognition and bearing fault condition monitoring. utilizing a 90nm CMOS process, employing the Cadence IC Suite for both the schematic and physical design stages. Comparative analysis of post-layout simulation results with an equivalent software based classifier affirms the accuracy of the modeling and design methodologies employed.