Comparative energy awareness and performance analysis of ARM and RISC-V SHA-256 hardware acceleration on the RP2350

FPGA validated RISC V system on chip with a custom systolic array accelerator for edge AI inference

A complete FPGA-validated RISC-V SoC in which a five-stage RV32IM processor works alongside a custom systolic MAC array, and two propositions are formally proved that the output-stationary schedule reduces computation cycles by a naïve, unblocked sequential CPU execution.

A Configurable FPGA SIMD architecture for FSM-oriented software testing acceleration

Equivalence of XOR and XNOR in differential cryptanalysis: application to SCAN-C

SCAN-C is a lightweight block cipher featuring a hybrid Feistel-SPN structure designed for Controller Area Network (CAN) security. This work presents the first full-round differential cryptanalysis of SCAN-C, demonstrating that its unique XNOR-based key mixing provides no additional security margin. We also prove that XNOR-based mixing is structurally equivalent to standard XOR mixing, as the corresponding difference distribution tables (DDTs) differ only by a permutation of indices. Utilizing an SMT-based automated search, we identify optimal differential clusters, including a 9-round distinguisher with a probability of 2-51.30\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2^{-51.30}$$\end{document}. By extending these results, we show that the complete internal key state can be recovered through the recovery of all 12 round keys, requiring around 255\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2^{55}$$\end{document} chosen plaintexts and 269\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2^{69}$$\end{document} encryptions. Our results confirm that the current 12-round specification is insufficient for security and is the first to show that differential cryptanalysis is equivalent under both XOR and XNOR difference definitions.

Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms

To satisfy the low-overhead and high-throughput requirements of embedded computing platforms executing cryptographic workloads, this study presents a high-performance RISC-V CPU IP core compatible with the standard RV32IM architecture. Instead of introducing dedicated cryptographic instructions, the proposed design enhances the execution efficiency of algorithms such as SM3 and SM4 through microarchitectural optimization of arithmetic units. A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput, while an enhanced radix-4 SRT divider incorporating leading-zero detection, result caching, and dynamic iteration control is proposed to reduce division latency. All modules are implemented in Verilog and integrated into a five-stage RISC-V pipeline. Functional verification is performed using a complete RVM instruction test suite, followed by FPGA-based performance evaluation. Experimental results demonstrate that the multiplier generates 64-bit results within a single clock cycle in 32-bit scenarios, reducing latency by more than 70% compared with conventional Wallace-tree implementations. The proposed architecture provides an efficient computing platform for secure embedded systems and offers implementation references for real-time signal processing, communication security, and electromagnetic information systems.

Branch-Free Binary128 Multiplication: SRMA Implementation with SSE2 Instructions and Kintex-7 Validation

In the modern world, 128-bit binary arithmetic is essential for achieving high numerical accuracy but remains expensive to implement in processors. This research presents an optimized, reduced-clock-cycle approach for performing 128-bit floating-point calculations on Field-Programmable Gate Arrays (FPGAs) using the SRMA architecture. The SRMA-focused implementation not only reduces execution time but also decreases energy consumption on Kintex-7 FPGA boards. Yet, today most of the processors are x86-64 CPU's which don't support floating point 128-bit calculations natively. On high performance processors, these generic methods trigger delayed pipelines and branch mispredictions, leading to longer clock cycles and increased energy. To unlock a processor's full potential, bridging the gap between slow software emulation and hardware support is a necessary task. The SRMA algorithm works on mantissa computations where it handles the branch-free arithmetics, where traditionally Generic algorithms use heavy branch-pipelining leading to unnecessary clock-cycles. This approach highlights the split-mantissa, an advanced approach where the mantissa of the scientific computations are split accordingly and then appended for minimal error. There is a bottleneck where software uses generic code that ignores the strengths of modern CPUs. Our ultimate goal is to run at speeds that make it practical for scientific computing at lower cost.

A Survey of AES-256 and SHA-256 Hardware Architectures on FPGA

In the present day, data confidentiality and integrity are among the major concerns in the embedded and communication systems and hardware-based cryptographic systems are playing a significant role in this regard. Moreover, the flexible features of FPGA implementations of cryptographic algorithms, such as greater performance, higher parallelism, and greater protection for sensitive data, are better than software-based approaches. This survey discusses the latest FPGA-based architectures of the AES-256 and the SHA-256, along with the design methodologies, optimization techniques and integration strategies. An analysis of existing studies is conducted to understand the pros and cons of various architectures, resource usage, throughput and implementation methods. The survey reveals that most current designs focus on optimizing only one aspect of encryption and hashing separately, whereas integrated designs may require extra hardware because of the duplicated control and interface logic. From these observations, it can be deduced that an efficient resource usage, scalability and secure hardware implementation is possible by integrating the AES-256 and SHA-256 components into a modular FPGA architecture.