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Author

N. Ramavenkateswaran

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Jul 2026

Power estimation in VLSI circuits: pre- and post-synthesis analysis with interpretable generalized additive neural networks

Development of a robust preprocessing framework using the CRCHEKF to handle noisy and incomplete data; design of an IGANN that explains the contribution of each feature to power dissipation; integration of the PSOA for adaptive parameter tuning to enhance accuracy and generalization provide a unified and transparent po...

T. Thyagaraj, N. Ramavenkateswaran, Madhusudan Kulkarni et al. · 0 citations
#edge computing Open access Aug 2026

FPGA validated RISC V system on chip with a custom systolic array accelerator for edge AI inference

A complete FPGA-validated RISC-V SoC in which a five-stage RV32IM processor works alongside a custom systolic MAC array, and two propositions are formally proved that the output-stationary schedule reduces computation cycles by a naïve, unblocked sequential CPU execution.

Srujan Sateesh Kalagi, K. R. Vinay Kumar, Shashank Dharamshetty et al. · 0 citations

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