Aug 2026· International Test Conference in Asia· pp. 1-6· 0 citations· 20 references
Abstract
As CMOS technology continuously advances and integration density steadily increases, the susceptibility of Static random-access memory (SRAM) cells to charge-sharing-induced Double-Node Upsets (DNUs) triggered by aerospace particles is significantly exacerbated. To address the formidable challenge of balancing radiation hardness and high-speed performance, this paper proposes URDT16T, a 16-transistor Radiation-Hardening by Design (RHBD) SRAM cell with high reliability, featuring a fully symmetric node-isolation topology. By effectively restricting the number of sensitive nodes and optimizing low-impedance discharge paths, the proposed design achieves 100% Single-Node Upset (SNU) recovery and 83% DNU tolerance, with a critical charge (Qc) exceeding 120 fC. Performance benchmarking reveals that URDT16T achieves an ultrafast Read Access Time (RAT) of 20.92 ps, representing an average reduction of 48.68% compared to nine state-of-the-art RHBD cells. Furthermore, the cell exhibits superior stability with a Hold Static Noise Margin (HSNM) of 442 mV, achieving the highest comprehensive Electrical Quality Metric (EQM) among compared designs. Robust operation is verified across extensive process-voltage-temperature (PVT) variations, demonstrating its steady performance in extreme environments and positioning URDT16T as a highly competitive solution for reliability-critical aerospace applications.
This paper proposes a feedback-enabled 10T FinFET based static random-access memory (SRAM) cell for low-power and high-speed operation in 10-nm technology node. With the scaling up of technology in SRAM, there are issues to consider with regards to power consumption, access delay, leakage, noise sensitivity, and reliab...
J. R. S. Kulothungan· Journal of Intelligent Decis...· 0 citations
Static Random Access Memory (SRAM) remains the dominant on-chip memory technology, occupying over 50% of chip area in modern microprocessors and serving as the backbone of cache hierarchies, register files, and AI accelerators (Evolution of SRAM Architectures, 2026). As CMOS technology scaling approaches fundamental ph...
Shivani Patel, Mrs. Deepali Sahu, Mr. Deepak Sahu· International Journal of Adv...· 0 citations
This paper presents the design and comprehensive analysis of a low-power ten-transistor (10T) static random-access memory (SRAM) cell implemented in a 16 nm FinFET technology with a nominal supply of 0.8 V. The proposed cell decouples the read port from the storage core using a two-transistor single-ended read stack, e...
Shivani Patel, Mrs. Deepali Sahu, Mr. Deepak Sahu· International Journal of Adv...· 0 citations
The aggressive scaling of complementary metal-oxide-semiconductor
(CMOS) into the deep nanometre regime has increased leakage power and reduced stability in
conventional static random-access memory (SRAM) cells, posing issues for ultra-low-power
applications. This study offers a fin-field effect transistor (FinFET)...
Ekta Jolly, Vijay Kumar Sharma, A. Bhardwaj· Micro and Nanosystems· 0 citations
This work puts forward a single bitline Schmitt-Trigger based Radiation Hardened 15T SRAM cell that aids immunity against radiation disturbances. The proposed cell demonstrates recovery from simultaneous disturbances affecting the storage node pair, thereby providing resilience against SEUs and SEMNU. The proposed cell...
Snigdha Jain, Neeta Pandey· International Symposium on V...· 0 citations
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