Stability and Leakage Optimization for an SRAM Cell Using FinFET Technology

Abstract

The aggressive scaling of complementary metal-oxide-semiconductor (CMOS) into the deep nanometre regime has increased leakage power and reduced stability in conventional static random-access memory (SRAM) cells, posing issues for ultra-low-power applications. This study offers a fin-field effect transistor (FinFET)-based 12-transistor (12T) SRAM cell with circuit-level leakage reduction. A stacked FinFET configuration is placed between the pull-up network (PUN) and the pull-down network (PDN) to prevent sub-threshold leakage while retaining functionality. The suggested FinFET-based 12T SRAM cell is tested using a predictive technology model (PTM) for a 7nm multi-gate FinFET technology node, a 0.7V power supply, and 27°C temperature. The simulation results show a significant reduction in leakage power and better read/write latency when compared to the conventional 6T SRAM design and existing FinFET-based SRAM designs The static noise margin (SNM) is estimated using the butterfly approach and improved for the proposed FinFET-based 12T SRAM cell. Monte Carlo simulations under ±10% process, voltage, and temperature (PVT) fluctuations show robustness despite large variations. The electrical quality metric (EQM) indicates greater overall performance. The proposed FinFET-based 12T SRAM cell balances power, performance, and stability, making it ideal for ultra-low power electronic applications.