FinFET-Based Low Power SRAM Cell Design

Abstract

This paper presents the design and comprehensive analysis of a low-power ten-transistor (10T) static random-access memory (SRAM) cell implemented in a 16 nm FinFET technology with a nominal supply of 0.8 V. The proposed cell decouples the read port from the storage core using a two-transistor single-ended read stack, employs differential write access with a stacked sleep footer to suppress standby leakage, and thereby overcomes the read-stability-versus-writeability contention that limits conventional six-transistor (6T) cells at scaled nodes. Simulated results at 27 °C show hold, read, and write static noise margins of 318 mV, 304 mV, and 296 mV respectively—the read margin representing a 105% improvement over the 6T cell—while standby leakage falls by 42.8% to 12.3 nW, read-access energy by 33.8% to 0.94 fJ, and read delay by 21.2% to 41 ps. A supply sweep from 0.5 V to 0.9 V confirms correct near-threshold operation with quadratic power scaling, and process-corner analysis at −40 °C to 125 °C verifies robust 6σ yield margins. The findings demonstrate that port-decoupled FinFET SRAM with footer stacking delivers simultaneous improvements in stability, energy, and speed relative to 6T, 8T, and 9T baselines, making it a strong candidate for on-chip caches and energy-constrained embedded memories.