Aug 2026· 2026 10th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT)· pp. 1-6· 0 citations· 12 references
Abstract
This paper proposes and demonstrates a new ADC (Analog-to-Digital Converter) architecture based on a binary search strategy. The proposed topology uses a single voltage divider to generate the reference for comparison with the input sample. Depending on the comparator’s output, the maximum or minimum levels of the voltage divider is updated accordingly, generating a new reference. The resulting circuit is simple, with few components and only two resistors for any bit precision. We present a proof-of-concept breadboard implementation with off-the-shelf components. The experimental results exhibit a consistent behavior with respect to mathematical simulations. In addition, this paper presents a clear description of the circuit operation, supported by a mathematical analysis that enables its design and implementation.
This work presents a switching scheme for singleended SAR ADCs that embeds a fully passive single-ended-todifferential converter within the sampling phase, eliminating the need for an active front-end. The proposed approach requires only two reference voltages and incorporates a common mode attenuation technique that d...
Jorge Angarita-Pérez, H. Hernández, A. Pena-Perez et al.· Symposium on Integrated Circ...· 0 citations
This paper presents the development, implementation, and characterization of a new high-resolution Digital-to-Time Converter (DTC) based on the Vernier architecture , implemented on a Field-Programmable Gate Array (FPGA). The main proposed improvement is overcoming the dynamic range limitation of the Vernier topology,...
Bernard Andrade Lucas, D. M. Colombo, T. P. Corrêa et al.· 2026 10th International Symp...· 0 citations
This paper presents a 6-to-12 bit resolutionreconfigurable charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) with a wide differential input range of $\pm 2.5 ~\mathrm{V}$. The proposed architecture enables programmable resolution (6, 8, 10, and 12 bits) by selectively activating p...
Anderson V. Backes, Davi S. Castro, A. L. Aita et al.· Symposium on Integrated Circ...· 0 citations
This paper presents a circuit schematic level design and functional simulation of six stage, 1 bit per stage CMOS Pipeline analog to digital converter (ADC) in Cadence Virtuoso. Each stage comprises sampling, binary threshold comparison, reference selection, subtraction and nominal gain of two residue amplification. Th...
Kuldeep Singh, Piyush Kumar, Ankur et al.· International research journ...· 0 citations
Timing errors represent a fundamental challenge in high-speed analog-to-digital converters (ADCs). This paper presents a frequency-interleaved architecture with inherent robustness to timing errors. The frequency interleaving is achieved by an embedded analog Fourier transform (AFT), allowing accurate channel spacing....
Xing-Chen Chao, Yun-Qiang Xu, Qiang Yu et al.· 0 citations
This paper presents a dual-mode switchable cascaded integrator-comb (CIC) filter with a wide decimation range for sigma–delta analog-to-digital converters (ADCs), enabling flexible adjustment of the output frequency rate and bandwidth. The proposed filter features two modes that can be switched according to power and p...
Xiao-Liang Ji, Peng Wang, Lu-Lu He et al.· Electronics· 0 citations
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