A 10-Bit Single-Ended SAR ADC with a Hybrid RC-DAC and Built-in Passive Differential Conversion

Abstract

This work presents a switching scheme for singleended SAR ADCs that embeds a fully passive single-ended-todifferential converter within the sampling phase, eliminating the need for an active front-end. The proposed approach requires only two reference voltages and incorporates a common mode attenuation technique that decreases comparator input common mode variations throughout the conversion process, thereby reducing dynamic offset and non-linearity. To further minimize silicon area and routing complexity, the scheme is implemented using a differential hybrid RC-DAC. The proposed architecture is validated through post-layout simulations of a 10-bit, 16 MS/s synchronous SAR ADC in 65 nm CMOS. The results show a typical ENOB of 9.514 bits at a Nyquist-rate input, together with a compact active area of 0.0028 mm2 and a Walden figure of merit of 16.51 fJ/Conv. - step, making the proposed solution suitable for multi-channel sensing applications.