High Dynamic Range FPGA-Based Vernier Digital-to-Time Converter

Abstract

This paper presents the development, implementation, and characterization of a new high-resolution Digital-to-Time Converter (DTC) based on the Vernier architecture , implemented on a Field-Programmable Gate Array (FPGA). The main proposed improvement is overcoming the dynamic range limitation of the Vernier topology, which is typically restricted to a single phase-coincidence cycle. Through the implementation of phase counters for both coarse and fine cycles, the proposed topology achieved a greater maximum number of bits without compromising resolution. Two versions of the circuit were synthesized and experimentally validated: one with a temporal resolution of 990 ps and another of 12.5 ps. The characterization process was fully automated using Python scripts and VISA protocol communication with a digital oscilloscope. The results demonstrate excellent linearity, with differential nonlinearity (DNL) ranging from -0.43 and 0.41 LSB, and Integral Nonlinearity (INL) from -0.59 to 0.67 LSB for the 990ps version, and the use of less than 1% of the FPGA’s capacity. Most notably, it achieves a maximum range of up to 26 bits at a 12.5 ps resolution, resulting in a dynamic range of 156 dB. Confirming the viability of the proposed topology for applications that require high precision and a wide dynamic range in the time domain.