Design and Pre-Layout Simulation of a 6-bit CMOS Pipeline ADC

Abstract

This paper presents a circuit schematic level design and functional simulation of six stage, 1 bit per stage CMOS Pipeline analog to digital converter (ADC) in Cadence Virtuoso. Each stage comprises sampling, binary threshold comparison, reference selection, subtraction and nominal gain of two residue amplification. The ideal stage transfer is derived and used to clarify bit significance, code formation, and pipeline timing delay. AC, DC, and Transient simulation of schematics of operational amplifier, sample and hold circuit, comparator, residue path and cascaded stage responses. The analyzed waveforms demonstrate block level operation and stage wise bit generation at a sampling rate of 10kS/s.