A 6-to-12B Resolution-Reconfigurable Multi-Voltage Domain Charge-Sharing SAR ADC for IoT Microcontroller Applications

Abstract

This paper presents a 6-to-12 bit resolutionreconfigurable charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) with a wide differential input range of $\pm 2.5 ~\mathrm{V}$. The proposed architecture enables programmable resolution (6, 8, 10, and 12 bits) by selectively activating portions of the capacitive DAC array, allowing dynamic trade-offs between resolution, power consumption, and conversion speed. Reducing the programmed resolution decreases both the effective sampling capacitance and the number of SAR cycles, enabling higher sampling rates, wider signal bandwidth, and improved compatibility with weak sensor signal sources. Designed in a 22 nm CMOS technology with a 2.5 V analog supply and a 0.8 V digital domain, the ADC achieves a peak ENOB of 10.87 bits at 1 MS/s. In the 6-bit configuration, the sampling rate increases to $\mathbf{1. 67 ~ MS} / \mathrm{s}$ while power consumption decreases from $\mathbf{109.7} \mu \mathbf{W}$ to $\mathbf{49.4} \mu \mathbf{W}$, achieving a FoM of 58.6fJ/conversion - step.