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Deep Learning Applications for Circuit Optimization and Hardware Organization

Sep 2026 · Zenodo (CERN European Organization for Nuclear Research)
VLSI and FPGA Design Techniques

Abstract

Abstract Traditional Electronic Design Automation (EDA) logic synthesis struggles with NP-hard state-space explosions as hardware scales to billions of gates. This paper explores deep learning paradigms specifically Graph Neural Networks (GNNs), Reinforcement Learning (RL), and generative transformers to accelerate digital circuit optimization and hardware organization. By modeling netlists as directed graphs, GNNs accurately predict wire delays and power consumption prior to physical routing. Concurrently, RL agents discover non-intuitive logic rewrite sequences on And-Inverter Graphs that outperform classical greedy algorithms, while generative models automate functional specification-to-gate translations. Synthesizing these methodologies demonstrates how AI mitigates computational bottlenecks, automates Power-Performance-Area (PPA) trade-offs, and scales next-generation hardware design.

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