Learning to Route On-Chip: A Survey of Machine Learning-Based Routing in Networks-on-Chip and Its Hardware Overheads
TL;DR
This survey reviews machine-learning-based NoC routing across a 48-study evidence base, and identifies three recurring gaps: limited scalability beyond small meshes, missing deadlock-freedom guarantees for learned policies, and over-reliance on synthetic traffic.
Abstract
Network-on-Chip (NoC) fabrics are the dominant interconnect for many-core processors, yet widely used routing methods—dimension-order routing and turn-model-based adaptive variants—assume mostly local, low-variance congestion. Modern workloads generate dense and bursty traffic that breaks these assumptions, motivating data-driven routing. Following a PRISMA-ScR protocol across five databases (2015–2026), this survey reviews machine-learning-based NoC routing across a 48-study evidence base, where path selection is posed as a Markov Decision Process and addressed with reinforcement learning and supervised/unsupervised regression rather than fixed analytic rules. We contribute a tripartite taxonomy organizing prior work by learning paradigm—mapped onto four empirical classes: tabular Q-learning, deep reinforcement learning, hybrid approaches, and supervised CNN-based prediction—transmission medium (planar/3D electrical and photonic NoCs), and multi-objective evaluation criteria (latency, throughput, energy, thermal budget, aging, fault tolerance). We ground comparisons in cycle-accurate simulation, FPGA/ASIC synthesis and its hardware overheads, feature-engineering and data-collection pipelines, and the accuracy metrics (RMSE, R2, error %) reported for learned predictors. We identify three recurring gaps: limited scalability beyond small meshes, missing deadlock-freedom guarantees for learned policies, and over-reliance on synthetic traffic, and outline future directions including graph neural networks, federated learning, spiking models, and runtime Pareto-front optimization for deployable, verifiable routing.
