Machine Learning-Assisted Optimization of CMOS VLSI Circuits for Low-Power and High-Speed Applications

Abstract

Scaling of complementary metal-oxide-semiconductor (CMOS) technology into the deep-nanometre regime has made the simultaneous minimisation of power and propagation delay one of the hardest problems in very-large-scale integration (VLSI) design. Supply voltage, threshold-voltage assignment, transistor sizing, body biasing and buffer insertion interact non-linearly, and the design space grows combinatorially with circuit size, so exhaustive SPICE-based exploration is intractable beyond small blocks. Classical metaheuristics such as simulated annealing and genetic algorithms handle the non-convexity but remain simulation-bound: every candidate must be evaluated by a costly simulator. This paper presents a machine learning-assisted optimisation framework that replaces most simulator calls with a learned surrogate, decoupling search cost from simulation cost. A graph neural network that consumes the netlist as an attributed graph is fused with a gradient-boosted regressor over scalar descriptors through a deep ensemble, which also yields a calibrated predictive uncertainty. A constrained NSGA-II search runs over the surrogate; an active-learning loop returns only high-uncertainty candidates to the simulator, and a verification stage re-simulates the Pareto set under process corners and Monte-Carlo variation. On eight digital benchmarks spanning arithmetic, control and datapath structures, the framework attains a mean power reduction of 27.4 % and a mean critical-path delay reduction of 18.6 % against a reference sizing — a 40.8 % improvement in power-delay product — while requiring roughly twenty times less wall-clock time than NSGA-II applied directly to SPICE. Surrogate accuracy reaches 2.7 % mean absolute percentage error for power and 2.4 % for delay. Ablation studies isolate the contribution of the graph encoder, the uncertainty-guided sampling policy and the ensemble, and a SHAP attribution analysis shows that supply voltage, critical-path sizing and threshold-voltage assignment dominate the learned power model, consistent with established device physics.