A Schematic-Level Digital Near-Memory Computing Architecture Utilizing 1T3R Memristor Arrays and Pipelined MAC for Pattern Recognition

Abstract

The traditional von Neumann architecture faces a severe memory wall bottleneck in modern data-intensive artificial intelligence applications. Memristor-based Computing-in-Memory (CIM) is a promising approach to reduce data movement, but conventional analog CIM remains vulnerable to read noise, sneak path currents, device variation, and the area and power overhead of high-resolution Analog-to-Digital Converters (ADCs). This work presents a schematic-level digital near-memory computing architecture based on a 1-Transistor-3-Resistor (1T3R) bit-slicing scheme for 3-bit signed weight storage. Each weight is mapped to three binary memristor states using two's complement representation, and the sensed digital outputs are processed by a low-bit pipelined Multiply-Accumulate (MAC) and Rectified Linear Unit (ReLU) backend. This design avoids high-resolution analog current readout and shifts the main computation to compact digital logic. The memristor array, write-inhibit and read control scheme, and digital processing blocks are implemented and functionally verified at schematic-level in Cadence Virtuoso using the open-source SkyWater 130 nm Process Design Kit (PDK) at a nominal 1.8 V supply. For system evaluation, a Python simulation framework is developed to incorporate the same low-bit quantization, signed weight mapping, finite bit digital arithmetic, and modeled device nonidealities. Hardware-aware simulations on Modified National Institute of Standards and Technology (MNIST) indicate that the proposed architecture can maintain functional classification capability under 3-bit weight and 2-bit input constraints. The reported macro power, performance, and area values are first-order projections from schematic simulations and scaling assumptions. Layout implementation, parasitic extraction, and post-layout validation remain future work.