An Updatable Nonvolatile Multi-bit Memory Array Core for Compute-in-memory Architectures

Abstract

This paper proposes a novel compute-in-memory architecture comprising multi-valued memory units using binary nonvolatile memory devices (NVMs) for brainmorphic circuits. The proposed architecture employs parallel-connected binary nonvolatile memory devices with thermometer-code representation to mitigate the impact of write errors while enabling addition and subtraction of memory values. The feedback write scheme conducts addition and subtraction of memory values on-chip across an array of multi-valued memory units. In this paper, we consider the implementation of voltage-controlled MRAM (VC-MRAM), which offers high endurance and low-voltage operation, making it suitable for brainmorphic hardware. To verify the circuit operation, we fabricated a CMOS-integrated test chip. This test chip consists of a single memory unit and a feedback write circuit, where the VC-MRAM devices were replaced with NMOS pseudo-resistive transistors to emulate NVM resistance states. Measurements showed less than 5% error compared to SPICE simulations, confirming accurate memoryto-PWM conversion. Numerical analysis further demonstrated an $\mathbf{8 7 \% - 9 5 \%}$ discrimination probability under 5% resistance variation. These results show the suitability of the architecture for multi-valued weight updates in robust brainmorphic systems.