Modern edge devices increasingly require real-time adaptation to their environment without relying on cloud-based updates, which can introduce latency and security risks. To meet these demands, memory-augmented neural networks (MANNs) have gained traction for enabling adaptive on-device learning. Hardware implementations of MANNs commonly use non-volatile memory-based ternary content-addressable memory (TCAM), but their discrete outputs and write-verify steps limit compatibility with gradient-based learning. This work introduces analog in-memory distance computing (AIMDC), a unified architecture based on indium gallium zinc oxide (IGZO) thin-film transistors that performs both embedding extraction and similarity search using analog capacitive units (ACUs). By producing continuous, differentiable outputs directly from analog embeddings, AIMDC enables hardware-in-the-loop on-device representation learning without additional processing. We demonstrate energy-efficient one-shot learning accuracy comparable to a graphics processing unit but with up to a 576× improvement in energy efficiency. The high retention and endurance of the IGZO-based ACUs establish AIMDC as a scalable and robust solution for high-throughput, low-energy edge learning.
This work presents a schematic-level digital near-memory computing architecture based on a 1-Transistor-3-Resistor (1T3R) bit-slicing scheme for 3-bit signed weight storage and indicates that the proposed architecture can maintain functional classification capability under 3-bit weight and 2-bit input constraints.
Zeyuan Hou, Xiao-Meng Wang, Yang Yi· Journal of Electronics and E...· 0 citations
This work introduces MITRA, a reconfigurable magnetic tunnel junction-based in-memory architecture that leverages stochastic computing (SC) to implement a broad class of transcendental and nonlinear functions directly within memory.
Farzad Razi, M. Moghadam, M. Najafi et al.· International Symposium on L...· 0 citations
A comprehensive hardware-aware design framework for systematically mapping algorithmic workloads onto IMC architectures, using the discrete Fourier transform (DFT) as a case study and a novel mapping scheme that reduces energy consumption per computation by 53% compared with conventional mapping techniques is introduce...
Sofia Tatidis, P. Nielsen, Liang Liu et al.· 0 citations
Charge-CIM addresses the bottleneck in ACiM accelerators by using switched-capacitor charge redistribution as a unified computing and conversion substrate, reducing both standalone converter overhead and intermediate ADC invocations.
Zihao Xuan, Ye-Wen Li, Jia Chen et al.· 0 citations
An analog CiM accelerator based on the SMX6 format, which extends the block floating-point representation with a lightweight microexponent shared by pairs of values is presented, demonstrating that micro-exponent-aware analog CiM with configurable granularity is an effective and practical design point for energy-effici...
Wonkyung Han, Dohyun Kim, Jihoon Park et al.· International Symposium on L...· 0 citations
Current-domain compute-in-memory (CIM) architectures offer a promising pathway to reduce data movement and eliminate costly data conversion overheads in edge AI systems. However, conventional resistive crossbar implementations rely heavily on peripheral circuits such as analog-to-digital converters (ADCs), which domina...
K. K. Gupte, De-Gang Chen, Cheng Wang· Midwest Symposium on Circuit...· 0 citations
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