An Area-Optimized SRAM-Based CIM Macro with Capacitor-Reused SAR ADC Achieving 2048 GOPS for Neural Network Acceleration

Abstract

This paper presents a charge-domain analog compute-in-memory (CIM) macro that integrates accumulation and analog-to-digital conversion (ADC) using an unified capacitor architecture. By re-utilizing the same binary-weighted capacitor array for both multiply-and-accumulate (MAC) operations and successive approximation register (SAR) ADC, the design achieves high integration density and energy efficiency. The proposed macro is based on 9T1C SRAM bitcell and provides 4-bit precision for both inputs and weights. MAC operations are performed via conditional capacitor switching. This creates an analog voltage on a shared top plate, which is then digitized using a 5-bit SAR ADC. This capacitor reuse eliminates unnecessary capacitive digital-to-analog converter (CDAC) structures in the SAR ADC, reducing area and switching power while improving matching. Pre-layout simulations in a 65-nm CMOS technology node show a peak throughput of 2048 GOPS and an energy efficiency of 438 TOPS/W at a 1.2 V supply, while achieving $\mathbf{9 4 . 2 \%}$ accuracy on the MNIST dataset. This architecture enables scalable, low-power, high-throughput edge AI inference.