4.608-TOPS SRAM Based DCIM Macro with Hierarchical Accumulation for Quantized CNNs

Abstract

The proposed work presents a compact 48-transistor adder for energy-efficient multi-operand accumulation in a digital SRAM-based Compute-in-Memory (DCIM) architecture. During hierarchical adder-tree reduction, it uses an organized columnwise accumulation technique to reduce logic depth, switching activity, and interconnect overhead. In a 64-bank SRAM array (64×4), this architecture allows bit-serial accumulation of partial products from 4-bit activations and weights, enabling simultaneous vector-matrix multiplication appropriate for CNN inference. The DCIM macro, which is built using 65-nm CMOS technology, has an energy efficiency of 67.92 TOPS/W and a peak throughput of 4.608 TOPS. Its efficacy for high-performance edge AI acceleration is confirmed by evaluations on MobileNetV2, ResNet, and EfficientNet models.