S. Vishvakarma

4.608-TOPS SRAM Based DCIM Macro with Hierarchical Accumulation for Quantized CNNs

The proposed work presents a compact 48-transistor adder for energy-efficient multi-operand accumulation in a digital SRAM-based Compute-in-Memory (DCIM) architecture. During hierarchical adder-tree reduction, it uses an organized columnwise accumulation technique to reduce logic depth, switching activity, and intercon...

A Lightweight RISC-V SoC with Power-Optimized ALU and UART Interface for Smart IoT Applications

Embedded processors that can enable sophisticated features like real-time recognition and self-adaptability while adhering to strict power and area limits are necessary due to the Internet of Things (IoT) rapid expansion. The development of adaptable and energy-efficient p rocessing s ystems h as been made possible by...

Energy-Efficient SNN Accelerator with Event Scheduling for Visual Edge Intelligence

Spiking neural networks (SNNs) are progressively utilized for edge intelligence due to their replacement of dense multiply-accumulate (MAC) operations with sparse, eventdriven dynamics that are compatible with low-power hardware. Nonetheless, converting these benefits into effective item recognition and classification...

BE-IMC: Bit-interleave 8T SRAM based In-Memory Computing macro for AI edge devices

BRAIN-AD: A Bit-Serial, ReRAm-Empowered Digital Processing-In-Memory Macro for Autonomous Driving

Conventional processing-in-memory (PIM) architectures suffer from limited efficiency due to transistor-intensive adder trees and analog-to-digital converter (ADC) overhead. This work presents BRAIN-AD, a bit-serial, ReRAM-based digital PIM macro for energy-efficient autonomous driving assistance systems (ADAS). The pro...

HierCIM: A 16-Kb SRAM-Based Digital CIM Macro With Hierarchical Adder-Tree Accumulation for Edge CNN Inference

The growing demand for efficient deep-learning inference on edge platforms requires hardware that is both energy-efficient and practically implementable. This work presents a 16-Kb all-digital static random-access memory (SRAM)-based compute-in-memory (CIM) macro for low-bit CNN inference, featuring a hierarchical adde...