Vikash Kumar Sharma

4.608-TOPS SRAM Based DCIM Macro with Hierarchical Accumulation for Quantized CNNs

The proposed work presents a compact 48-transistor adder for energy-efficient multi-operand accumulation in a digital SRAM-based Compute-in-Memory (DCIM) architecture. During hierarchical adder-tree reduction, it uses an organized columnwise accumulation technique to reduce logic depth, switching activity, and intercon...