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Author

Vikash Vishwakarma

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Aug 2026

4.608-TOPS SRAM Based DCIM Macro with Hierarchical Accumulation for Quantized CNNs

The proposed work presents a compact 48-transistor adder for energy-efficient multi-operand accumulation in a digital SRAM-based Compute-in-Memory (DCIM) architecture. During hierarchical adder-tree reduction, it uses an organized columnwise accumulation technique to reduce logic depth, switching activity, and intercon...

Vikash Kumar Sharma, Vikash Vishwakarma, S. Vishvakarma · 0 citations
#edge computing Sep 2026

HierCIM: A 16-Kb SRAM-Based Digital CIM Macro With Hierarchical Adder-Tree Accumulation for Edge CNN Inference

The growing demand for efficient deep-learning inference on edge platforms requires hardware that is both energy-efficient and practically implementable. This work presents a 16-Kb all-digital static random-access memory (SRAM)-based compute-in-memory (CIM) macro for low-bit CNN inference, featuring a hierarchical adde...

Vikash Vishwakarma, Gopal R. Raut, Amit Mittal et al. · 0 citations

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