An Analog Frequency-Domain Systolic Array for Energy-Efficient AI Acceleration at the Edge

Design And Implementation Of An XNOR-Based Variable-Precision Object Detection Accelerator For Real-Time Edge AI Applications

This paper presents a hardware-efficient object detection accelerator based on XNOR-driven variable-precision computation for real-time edge artificial intelligence. The proposed network combines DenseToRes and transition layers to preserve feature information under aggressive quantization. Binary convolution is executed through XNOR and population-count operations, replacing most multiplier-based multiply-accumulate units. To maintain detection accuracy, the architecture supports 1-bit, 2-bit, and 8-bit modes so that sensitive layers can use higher precision while deeper layers operate at reduced precision. A parallel array of 64 processing elements performs multiple output-channel computations concurrently using an output-stationary dataflow. The accelerator integrates on-chip feature and weight memories, data-fetch units, batch normalization, RPReLU activation, quantization, pooling, and lightweight control logic. AXI-based interfacing enables integration with an embedded processing system and external memory. The resulting architecture reduces arithmetic complexity, memory bandwidth, and power consumption while supporting scalable real-time object detection on FPGA-based edge platforms.  

Design And Implementation Of An ADC/DAC-Free Walsh-Hadamard Transform Based Neural Network Accelerator Using Bit-Plane Processing

An ADC/DAC-free neural accelerator based on the Walsh-Hadamard Transform and bit-plane processing that offers a multiplier-free, converter-free, regular, and scalable solution for low-power edge intelligence.

A novel design of high throughput power efficient multiply accumulate unit

A Flexible FPGA-based Butterfly Engine for Accelerating Signal Processing and Machine Learning

Field-programmable gate arrays (FPGAs) have emerged as efficient accelerators for both neural network (NN) inference and digital signal processing (DSP) tasks, particularly on resource-constrained edge devices. While previous NN accelerators based on butterfly operations demonstrate significant acceleration for inference, they are inadequately suited for long sequences and lack support for bit-reversed access patterns, limiting their applicability to variable-length DSP workloads. Based on prior butterfly accelerators, this paper presents flexible butterfly engine (FlexBE), together with a co-designed NN architecture, Butterfly-based Signal Processing Net (BSPNet). The proposed system jointly supports signal pre-processing and butterfly linear (BL)-based NN inference under stringent resource constraints. FlexBE incorporates novel adaptive data switching networks, dynamic access control mechanisms, and an efficient bit-reversal module, enabling runtime reconfiguration of sequence lengths and degrees of parallelism. Implemented on an AMD ZCU104 FPGA running at \(300\) MHz, FlexBE computes four \(32\) k-point fast Fourier transforms (FFTs) in approximately \(15,360\) clock cycles. On challenging automatic modulation classification (AMC) datasets, BSPNet achieves accuracy comparable to GPU baselines. For single-batch inference, BSPNet with FlexBE is \(2.2\sim 3.1\times\) faster than prior butterfly-based accelerators; on the ZCU104, the end-to-end latency achieves speedups of up to \(4.92\times\) and \(2.89\times\) compared to an Intel Core i9 CPU and an NVIDIA RTX 3090 GPU, respectively.

FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity

FlexSpIM, a digital CIM architecture supporting arbitrary operand resolution and shape within a unified storage for weights and neuron states, is introduced, enabling a layer-level hybrid weight- and output-stationary dataflow, maximizing operand reuse and reducing costly on- and off-chip data movement during SNN execution.

RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions.

YOLOv3-tiny is widely used in edge-oriented object detection, but its deployment on resource-constrained platforms is limited by high computational cost and the limited flexibility of conventional processors. This paper presents a RISC-V-based acceleration framework for YOLOv3-tiny inference that combines a tightly coupled CPU-accelerator architecture with runtime-reconfigurable hardware support. A Hummingbird E203 core is integrated with a dedicated accelerator through the NICE interface, and 11 custom instructions are introduced for data movement, convolution control, and post-processing. The hardware adopts a runtime-reconfigurable systolic array supporting multiple convolution kernel sizes, together with activation, pooling, fully connected, and detection-oriented post-processing modules. The design is implemented on an Artix-7 FPGA and evaluated using a hardware-oriented YOLOv3-tiny workload, supplemented by module-level analysis and same-platform baseline comparisons. Experimental results show a 79.5% reduction in convolution execution time and a 4.89 × speed-up over the baseline RISC-V processor. Hardware-supported post-processing further reduces the cycle cost of sorting and IoU-related computation by 60.55% and 45.44%, respectively. These results demonstrate the effectiveness of the proposed processor-coupled acceleration architecture for YOLOv3-tiny-based detection inference on edge platforms.