A Low-Power Pipelined IEEE 754 Floating-Point Datapath for Energy-Efficient Neural Network Acceleration

A novel design of high throughput power efficient multiply accumulate unit

A High-Performance and Low-Resource Reconfigurable Hardware Implementation for Softmax in Transformer

The efficient implementation of the softmax is critical for optimizing transformer hardware accelerators. Unlike its role as a static, one-time classifier in convolutional neural networks (CNNs), softmax in transformers is core to achieving dynamic contextual awareness, generating attention weights that enable the model to focus on relevant information. Its high-frequency, large-scale execution across every layer makes the softmax a critical performance bottleneck, particularly when processing long sequences. Existing hardware implementations face two primary challenges: excessive resource consumption from the exponential (EXP) computation, and high latency induced by the softmax’s nonelementwise nature. This article proposes a domain-unified piecewise EXP approximation technique. This technique reduces the resource consumption of the EXP unit by 23% and its approximation error by 26%. Furthermore, the proposed design provides direct and efficient hardware-level support for the online softmax algorithm, significantly reducing latency. Under the TSMC 40-nm process, it achieves a $1.36\times $ improvement in area-normalized throughput. On a Xilinx KCU116 FPGA, LUT-normalized throughput improves by $1.26\times $ . Moreover, the proposed reconfigurable architecture substantially improves resource utilization. Finally, end-to-end evaluations confirm that the design strictly preserves native inference accuracy while delivering a notable 4.86% overall system-level latency reduction for Llama3-8B.

An Analog Frequency-Domain Systolic Array for Energy-Efficient AI Acceleration at the Edge

The results indicate that exploiting the inherent parallelism of analog computation offers a promising pathway toward ultra-low-power AI inference, making the proposed architecture a potential alternative for energy-constrained edge applications.

HyST-DNA: Hybrid SRAM-TCAM DNN accelerator with genetic optimization on FPGA

Edge intelligence applications demand high-throughput and energy-efficient hardware accelerators under strict power, latency, and resource constraints in real-time environments. Conventional compute-centric architectures rely heavily on sequential multiply-accumulate (MAC) operations and frequent off-chip memory access, resulting in high energy consumption, increased latency, and bandwidth bottlenecks. These limitations become more pronounced as neural network models scale in size and complexity. While Ternary Content-Addressable Memory (TCAM) offers an alternative through parallel associative search and constant-time pattern matching, it suffers from excessive power consumption and limited adaptability due to continuous match-line activation. This work proposes a hybrid SRAM-TCAM memory-centric deep neural network (DNN) architecture that integrates three tightly coupled subsystems. First, a two-layer autoencoder with ReLU activations compresses 128-bit input feature vectors to 32-bit latent codes, achieving a compression ratio η=4×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\eta = 4\times $$\end{document} and a 75%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$75\%$$\end{document} BRAM saving. Second an on-chip dual-port BRAM data-locality buffer exploits the compressed representation to eliminate inter-layer off-chip DRAM accesses in the critical inference path. Third, a 256×32\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$256 \times 32$$\end{document}-bit Ternary Content-Addressable Memory array provides O(1) parallel associative inference. A software-only Genetic Algorithm (GA) with Roulette Wheel Selection (RWS) optimizes TCAM configuration offline prior to FPGA deployment; the converged 8,480-bit chromosome is loaded once at startup and remain static during inference, adding zero dynamic power overhead. The proposed architecture, implemented on a Xilinx Artix-7 FPGA, achieves a 42.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$42.3\%$$\end{document} reduction in power compared to a conventional MAC-based baseline (120.5 mW vs. 208.7 mW), an end-to-end throughput of 108.47 Mops reflecting steady-state pipelined operation at 108.47 MHz (2.42×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2.42\times $$\end{document} speedup), and an inference accuracy of 95.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$95.3\%$$\end{document} – a 1.5%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.5\%$$\end{document} degradation attributable to quantization, evaluated on the benchmark dataset. Power figures are obtained from the Vivado Power Estimator tool (post-implementation) at nominal supply voltage of 1 V. These results demonstrate an efficient and scalable solution for next-generation edge AI inference systems.

A High-Efficiency, High-Accuracy Approximate Multiplier for DNN Accelerators

Multipliers dominate the critical path, power consumption, and silicon area of deep neural network (DNN) accelerators. This paper presents a high-efficiency 7-bit unsigned approximate multiplier tailored for DNN accelerators. Unlike conventional signed 8-bit designs—where the sign bit is handled separately via XOR—the proposed architecture directly adopts a 7-bit unsigned format. Based on distribution-aware approximation, the partial-product reduction stage is redesigned with exact compressor allocation, while a lightweight bit-flipping technique increases bit-level sparsity, reducing dominant partial products by over 50% with only small compensable errors. FPGA implementation shows strong hardware efficiency, achieving up to 28.7% reduction in logic resources and 13.4% lower dynamic power compared with recent high-accuracy approximate multipliers. DNN inference evaluation on representative models and datasets shows minimal accuracy degradation by 0.27% on LeNet–MNIST and competitive performance on more challenging tasks, outperforming PAM1 and PAM2 by $\mathbf{4 . 4 8} \boldsymbol{\%} \boldsymbol{-} \mathbf{4 . 7 5 \%}$ on LeNet–SVHN. These results demonstrate an effective balance between hardware efficiency and inference accuracy for energy-efficient DNN accelerators.

A 64-bit high-precision flash computing-in-memory architecture with a parallel input scheme