Smart Circuit Structure Learning for Digital Logic Optimization

Abstract

Abstract The increasing scale and interconnectedness of digital logic designs make it more difficult to examine their internal organization and determine where improvements can be made. Conventional Electronic Design Automation (EDA) methods generally depend on established algorithms and rule-driven procedures, which may become less manageable when many gates and signal dependencies have to be considered at the same time. This study proposes a graph-based machine learning approach in which Graph Neural Networks (GNNs) are used to study digital logic circuits and locate structural regions that could be considered for optimization. In the proposed representation, individual logic gates become graph nodes and the signal links between them become graph edges. Circuit information such as gate category, fan-in, fan-out, logic depth, signal paths, and connectivity will be extracted as features for the model. The investigation will determine whether a GNN can learn meaningful relationships from these circuit structures and use those relationships to highlight potential optimization targets. The anticipated outcome is a more informed assessment of graph-based learning as a supporting technique for digital circuit optimization. Keywords—Graph Neural Networks (GNNs), Digital Logic, Circuit Optimization, Electronic Design Automation (EDA), Machine Learning