Intelligent Digital Logic Circuit Optimization Through Graph Neural Networks

Abstract

Abstract The increasing complexity of digital logic circuits creates a need for effective methods of circuit analysis and optimization. Conventional Electronic Design Automation (EDA) techniques commonly depend on established algorithms and predefined rules, which can become difficult to apply to more complicated circuit structures. This study proposes the use of Graph Neural Networks (GNNs) to analyze digital logic circuits and identify possible optimization opportunities. In the proposed representation, logic gates are modeled as nodes while the connections among them are represented as edges. Circuit characteristics such as gate type, fan-in, fan-out, logic depth, signal paths, and connectivity will be considered as model features. The study will examine how GNN-based representations can recognize structural patterns and support the identification of circuits that may be improved. The expected results may provide a basis for using graph-based machine learning as a supporting approach to digital circuit optimization. Keywords—Graph Neural Networks (GNNs), Digital Logic Circuits, Circuit Optimization, Electronic Design Automation (EDA), Machine Learning