Learning Circuit Structures for Intelligent Digital Logic Optimization

Abstract

Abstract Digital logic systems become increasingly difficult to examine and improve as their structures grow in size and complexity. Traditional Electronic Design Automation (EDA) methods generally depend on established algorithms and rule-based procedures, which may become less convenient when many gates and signal connections must be considered together. This study proposes a graph-based machine learning approach using Graph Neural Networks (GNNs) to examine digital logic circuits and locate possible areas for improvement. In the proposed representation, individual logic gates are treated as graph nodes and the signal connections between them are treated as edges. Circuit information such as gate category, fan-in, fan-out, logic depth, signal paths, and connectivity will be extracted as model features. The investigation will determine whether a GNN can learn structural relationships within circuits and use those relationships to point out potential optimization targets. The expected outcome is a clearer basis for evaluating graph-based learning as a supporting technique for digital circuit optimization. Keywords—Graph Neural Networks (GNNs), Digital Logic, Circuit Optimization, Electronic Design Automation (EDA), Machine Learning