Application of Graph Neural Networks in Digital Logic Circuit Optimization

Abstract

Abstract Digital logic circuits are becoming increasingly complex, making efficient circuit optimization an important part of Electronic Design Automation (EDA). Traditional circuit optimization methods may require extensive computation and predefined rules when dealing with complex circuit structures. This study aims to investigate the application of Graph Neural Networks (GNNs) for analyzing and optimizing digital logic circuit structures. Digital circuits will be represented as graphs in which logic gates are treated as nodes and their connections as edges. Circuit features such as gate type, fan-in, fan-out, and logic structure will be considered as inputs to the GNN. The study will examine how these circuit representations can be used to identify patterns and possible areas for optimization. The study is expected to determine how GNN-based circuit representations can assist in identifying optimization opportunities and improving selected circuit characteristics. The findings may provide a basis for using graph-based machine learning approaches as an alternative or supporting method for digital circuit optimization.