A Lightweight RISC-V SoC with Power-Optimized ALU and UART Interface for Smart IoT Applications

Abstract

Embedded processors that can enable sophisticated features like real-time recognition and self-adaptability while adhering to strict power and area limits are necessary due to the Internet of Things (IoT) rapid expansion. The development of adaptable and energy-efficient p rocessing s ystems h as been made possible by the growing use of the RISC-V instruction set architecture (ISA). In order to facilitate effective peripheral interface and external device connections, we present a lightweight RISC-V-based system-on-chip (SoC) that integrates a UART communication module and an AMBA APB interconnection architecture. An improved arithmetic logic unit (ALU) that maximizes computing performance and minimizes power consumption is part of the suggested architecture. To enable standalone operation, the system additionally includes data memory and on-chip instruction. Using a Basys-3 FPGA platform, the design achieves resource utilization of 361 LUTs and 44 flip-flops with a power consumption of 9 mW, which is 96.96%, 82.69%, and 95.89% less than the current cores. Additionally, ASIC synthesis in a 28 nm technology node shows an area of 0.015mm2, power consumption of 0.5537 mW, and maximum operating frequency of 253 MHz reductions of 99.66%, 53.85%, and a $21.73 \times$ speedup then compared cores. In comparison to current state of the art IoT CPU designs, the results show that the suggested design provides a favourable trade-off between performance, power, and space.