Energy-Efficient SNN Accelerator with Event Scheduling for Visual Edge Intelligence

Abstract

Spiking neural networks (SNNs) are progressively utilized for edge intelligence due to their replacement of dense multiply-accumulate (MAC) operations with sparse, eventdriven dynamics that are compatible with low-power hardware. Nonetheless, converting these benefits into effective item recognition and classification systems is difficult because of the intricacies of training, memory bandwidth, and the disparity between frame-based sensors and spike-based processing. This work proposes a hardware-based SNN accelerator designed for realtime object classification a nd l ightweight o bject d etection. The architecture comprises three principal components: (i) a leaky integrate-and-fire (LIF) n euron d atapath w ith programmable decay, (ii) a time-multiplexed synaptic processing array optimised for sparse spike traffic, a nd (iii) a no n-chip e vent scheduler that reduces off-chip bandwidth by aggregating spike packets. The design is evaluated using a hardware-aware hybrid training strategy that combines ANN-to-SNN conversion with surrogategradient fine-tuning u nder e xplicit q uantization a nd temporal constraints. Software simulation results, obtained via a cycleaccurate PyTorch model calibrated to a 65 nm CMOS process at 200 MHz and 0.9 V supply, demonstrate competitive classification accuracy of 99.0% on MNIST and 89.6% on CIFAR-10, with energy per inference of 0.07 mJ and 0.39 mJ respectively—representing reductions of 2.9×-5.4× compared with a compact CNN on an embedded GPU—while sustaining sub-20 ms end-to-end latency under moderate sparsity conditions. These findings demonstrate that coordinated co-design of SNN models and accelerator microarchitecture can substantially reduce the practical gap between neuromorphic potential and deployable visual workloads.