This work presents a hybrid and light-weight machine learning (ML) based approach that combines a decision tree with linear regression to improve pre-routing delay estimations generated by the open-source RTL-to-GDSII tool OpenLane.
Abstract
Static Timing Analysis (STA) is a critical step in the design flow of digital integrated circuits, however, obtaining accurate delay estimations can represent a challenge when limited information regarding physical design is available. In response, this work presents a hybrid and light-weight machine learning (ML) based approach that combines a decision tree with linear regression to improve pre-routing delay estimations generated by the open-source RTL-to-GDSII tool OpenLane. The proposed model achieves an 80\% reduction in error compared to OpenLane's estimates, demonstrates a 71\% improvement even without utilizing OpenLane-specific parameters. Overall, this method offers an alternative to traditional delay propagation techniques and more complex machine learning models that is not only accurate, but is also over 300 times smaller, 2 times faster and offers a higher explainability.
DeepNC is a novel pre-verification surrogate module that pioneers the structural fusion of NC principles into a Graph Neural Network (GNN) for TSN configuration-space exploration, and significantly improves worst-case delay prediction accuracy over state-of-the-art learning-based methods.
This work presents a power-friendly framework for efficient manufacturing test of dynamic voltage and frequency scaling (DVFS)-based 3D Systems-on-Chip (SoCs). The proposed approach employs a through-silicon via (TSV)-based inter-layer test architecture to enable compact and high-speed delivery of test data across stac...
Leonidas Skaltsonis, Nikolaos V. Oikonomou, F. Vartziotis· Chips· 0 citations
Results show that port-state awareness combined with learned, controller-local policies can substantially reduce the decision-to-action latency of FRR, providing a practical path toward low-latency failure recovery in SDN migration scenarios.
Md. Imtiaz Ahmed, Yaser Al Mtawa· Network· 0 citations
Three-dimensional stacked ICs introduce new Design-for-Test (DfT) challenges due to high power density, routing congestion, and cross-tier connectivity constraints. In this work We propose 3D Joint-Scan, a tier-aware DfT architecture that extends the 2D Joint-scan framework to multi-tier 3D ICs and integrates reinforce...
Hilay Patel, Naman Kalra, Jaynarayan T. Tudu· 2026 IEEE 10th International...· 0 citations
An Energy Optimized Network Route Cluster Bandwidth (EONRCB) is an Enhanced Service Data Transmission (ESDT) model proposed in this paper to circumvent problems of data leakage and packet misinsertion and achieves higher energy efficiency, reduced congestion, and a longer network lifespan.
Sangeetha E, D. J· Journal of universal compute...· 0 citations
The scalability of multiprocessor networks on-chip is restricted by the performance of on-chip interconnects. Optical networks-on-chip (ONoCs) offer ultra-high bandwidth and energy-efficient solutions for these bottlenecks. Although 2D ONoCs have several advantages, scalability is a challenge because of limited chip ar...
Nathrao B. Jadhav, Bharat S. Chaudhari, P. Khandekar· Future Internet· 0 citations
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