DeepNC is a novel pre-verification surrogate module that pioneers the structural fusion of NC principles into a Graph Neural Network (GNN) for TSN configuration-space exploration, and significantly improves worst-case delay prediction accuracy over state-of-the-art learning-based methods.
Abstract
Time-Sensitive Networking (TSN) is critical to deterministic communication in safety-critical domains, with formal verification such as Network Calculus (NC) serving as the cornerstone for schedulability guarantees. However, during automated configuration-space exploration, repeated schedulability analysis consumes over 90% of the total configuration time, becoming the primary bottleneck for large-scale TSN configurations. To address this challenge, we propose DeepNC, a novel pre-verification surrogate module that pioneers the structural fusion of NC principles into a Graph Neural Network (GNN) for TSN configuration-space exploration. Rather than replacing formal verification, DeepNC acts as a high-speed pre-verification filter, reserving computationally expensive formal verification only for promising candidates. Extensive evaluations demonstrate that DeepNC significantly improves worst-case delay prediction accuracy over state-of-the-art learning-based methods, increasing the average $R^2$ by 55.8% and reducing the average MAPE by 65.3%. More importantly, its high-fidelity regression substantially reduces the number of formal verification calls during configuration-space exploration by 93.25%, while accelerating NC-based verification by more than two orders of magnitude.
Industrial automation is rapidly evolving toward flexible production. This transition requires networks to ensure the deterministic transmission of varying traffic sets across different production stages. Consequently, the system must be capable of rapidly analyzing whether fixed network resources can accommodate all service requirements prior to actual scheduling. While Time-Sensitive Networking (TSN) provides the deterministic transmission for such environments, existing schedulability assessments rely on exhaustive scheduling tests. However, the scheduling process is inherently an NP-hard constraint satisfaction problem, whose heavy computational overhead severely limits deployment agility. Therefore, it is critical to develop a method that can rapidly predict the constraint satisfiability of diverse traffic sets without repetitive and time-consuming scheduling. In this work, given the inherent graph-structured nature of network infrastructure and traffic patterns, we design a graph neural network model to explicitly capture complex spatial dependencies. As node attributes, sparse basic traffic features are distilled as expert knowledge and integrated, thereby enhancing prediction accuracy. When a traffic set is deemed unschedulable, we explore the traffic features and links with the greatest impact. Based on this, a feature-driven rerouting strategy is proposed to find a more schedulable traffic behavior. The evaluation results show that the model demonstrates the capability to process thousands of datasets within hundreds of microseconds, while guaranteeing a prediction accuracy of over 90% and an increase in the count of schedulable flows by about 25% compared to the standard Dijkstra’s shortest path algorithm baseline.
Qi-Ru Chen, Xinping Guan, Lei Xu et al.· IEEE Transactions on Network...· 0 citations
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7$\times$ on specific tasks; (2) in system-level design space exploration, top LLMs converge to the optimal configuration with higher reliability than random search, simulated annealing, and Bayesian optimization baselines (5/5 seeds vs. 0-4/5 at the same 24-round budget); (3) strategy-level specification changes remain unsolved for most models. Across the six models, generation and DSE rankings overlap moderately: the strongest code generator is not the fastest architecture optimizer, and the weakest code generator (MiniMax M2.7) still reaches the system optimum on 4 of 5 seeds. On the tasks in FinHardBench, difficulty tracks training data pattern availability more closely than abstraction level. FinHardBench is released as an open-source benchmark.
Weimin Fu, Hejia Zhang, Minghao Shao et al.· 0 citations
Autonomous racing exposes the sim-to-real gap under extreme operating conditions characterized by high speed, tight stability margins, and stringent real-time constraints. Although simulation is indispensable for development, controllers that perform well in simulation often degrade abruptly on physical platforms due to interacting effects of dynamics mismatch, estimation delay, and execution-layer latency. This paper frames sim-to-real transfer in autonomous racing as a full-stack, real-time systems problem. We introduce a structured three-layer perspective (Physical/Cyber/Execution) to analyze how mismatches propagate and amplify through closed-loop feedback. We present diagnostic metrics beyond nominal lap time, including performance flip, stability-oriented measures, sensitivity to delay and noise, and latency distribution characterization. Mitigation strategies are synthesized from a deployment-oriented viewpoint, emphasizing execution-aware and delay-aware design. Finally, we outline benchmarking guidelines that enable reproducible and fair sim-to-real evaluation under compute and timing constraints. The resulting framework clarifies cross-layer failure mechanisms and provides practical design principles for deployable autonomous racing systems operating near dynamic limits.
Hossein Maghsoumi, Yaser P. Fallah· arXiv.org· 0 citations
This work presents a comprehensive overview of the TSN deployment lifecycle, current challenges, limitations of existing tools, and future research directions for TSN deployment and management, and identifies key research gaps from a deployment perspective and provides guidance for the development of next-generation deployable TSN networks.
Rubi Debnath, Paul Pop, Silviu S. Craciunas et al.· 0 citations
This paper presents our experience deploying TianYan on Alibaba Cloud's global production WAN, which is, to the best of our knowledge, the first system for verifying non-deterministic convergence on a global production WAN. In daily operation, we rely on simulation-based configuration verifiers that assume a single converged data plane to ensure reliability and performance. However, non-deterministic convergence—where a configuration yields different converged data planes—undermines verification accuracy and has caused a production incident, motivating the need to analyze non-deterministic convergence itself. At scale, this is challenging because the analysis space grows exponentially with the number of routers. TianYan addresses this challenge with a key insight: by leveraging routing similarity among routers within the same group—a common fault-tolerance practice—it reduces exponential complexity from the number of routers to the number of groups, enabling efficient convergence analysis. Over a year of deployment, TianYan identified non-deterministic convergence in ~2% of all prefixes, exposed unnoticed design flaws, and improved simulation-based verification accuracy through integration. We share representative cases and evaluation results from our production WAN, distilling key operational lessons and practical guidelines for managing nondeterminism at scale.
Xing Fang, Fangdan Ye, Yifei Yuan et al.· Conference on Applications,...· 0 citations
Learned controllers are increasingly deployed inside hard real-time loops in automotive and industrial automation, where a safety case for the hard real-time controller path typically targets a zero-miss execution budget (with the standards-mandated WCET arguments). In this paper, we present CertiHybrid-B, an RTOS–FPGA co-architecture pairing a FreeRTOS-class host with a streaming FPGA datapath. This datapath executes a quantized neural forward pass, a hardware Lyapunov monitor, a Lyapunov-budget-aware controller-selector among a fast neural mode, a safety-filtered mode, and a robust LQR fallback, and an on-fabric safety filter that clips the neural action to a Lyapunov-decrease interval in the scalar-input case and to a heuristic per-channel relaxation in the multi-input case. Across cart-pole and quadrotor experiments with up to 100 seeds, we confirmed that CertiHybrid-B maintained a 0% deadline-miss rate and eliminated closed-loop divergence. In particular, it significantly reduced the tracking RMSE from 0.278 to 0.057 rad compared to the existing single-mode baseline, all within an ultra-low PL-internal datapath latency of 280–380 ns and under 12% resource utilization—reported as an analytical resource estimate cross-checked by an on-device ARM software-equivalent proxy rather than a post-route synthesis result—thereby supporting both the projected timing feasibility and the control stability of the hard real-time controller path.
