Aug 2026· IEEE International Conference on Embedded and Real-Time Computing Systems and Applications· pp. 125-133· 0 citations· 38 references
Abstract
CXL SSDs extend system memory using NAND flash, providing a scalable solution to the capacity and bandwidth limits of memory-intensive, multi-tenant cloud services. Since CXL SSDs are directly addressable by the CPU, SSD-internal prefetching is crucial for hiding flash-grade latency from the host. However, host-side paging fragments access patterns and breaks spatial locality in virtual addresses, rendering conventional address-based prefetchers ineffective in the context of CXL SSD. We identify evict correlation, where cache lines written back from the SSD's internal cache to flash within a short interval are likely to be re-referenced together by the host. By tracking data layout in flash pages and the SSD cache eviction history, this correlation can be detected, exploiting out-of-place updates and sub-page mapping in flash. Combined with a dynamic SSD cache allocation across tenants, our approach reconstructs access locality and reduces overall reference latency. Experiments on HPC and AI/ML workloads demonstrate accurate prefetching and efficient SSD resource utilization.
LM-CXD bridges the semantic gap between the serving engine and the device, and exposes NAND-to-DRAM progress to the serving engine, and uses device DRAM as a GPU-accessible buffer to hide NAND latency under limited device DRAM.
Hyunsun Chung, Taewan Noh, Minji Kim et al.· 0 citations
The BASIC Prefetcher is proposed, which recovers application-level I/O patterns by classifying requests into size-based bins and modeling temporal bin transitions with a lightweight Markov-chain framework and achieves up to 89% prediction accuracy on sequential workloads and 70% on highly random workloads, including AI...
Han Jang, Dongjun Lee, Youngbin Jin et al.· Proceedings of the 19th ACM...· 0 citations
A Lightweight Cache Buffer Management (LCBM) strategy that avoids precise frequency tracking altogether and reduces the average read latency and the write response time, while eliminating the metadata overhead of counter- and LRU-based designs is introduced.
CXL-SSDs promise memory-semantic access to NAND-scale capacity through a small in-device DRAM cache, but scarce hardware makes emulation central to CXL-SSD research. Cylon, a state-of-the-art emulator, runs workloads in a VM, intercepting DRAM misses to inject NAND latency. We show this VM machinery adds over 3$\mu s$...
Hyunsun Chung, Seongho Bong, H. Kim et al.· 0 citations
Persistent memory (PM) bridges the latency and cost gap between DRAM and SSDs. Within the DRAM–PM–SSD hierarchy, deploying key-value-separated key-value stores (KV-separated stores) is imperative for optimizing system longevity and performance. This architecture mitigates SSD write amplification and preserves PM endura...
Hui Sun, Ya-Jie Deng, Xiao Qin et al.· IEEE transactions on compute...· 0 citations
Remote object stores are widely used in public and private clouds for their simplicity and reliability, but their high latency and transfer costs make local caching essential. While RAM caches are common, they become prohibitively expensive at scale, leading to the adoption of flash-based (SSD) caches. However, convent...
J. Ramsden, Sam Cheng, Hans Holmberg et al.· Proceedings of the 19th ACM...· 0 citations
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