Paging-Resilient Prefetching in Flash-Based CXL SSDs
CXL SSDs extend system memory using NAND flash, providing a scalable solution to the capacity and bandwidth limits of memory-intensive, multi-tenant cloud services. Since CXL SSDs are directly addressable by the CPU, SSD-internal prefetching is crucial for hiding flash-grade latency from the host. However, host-side paging fragments access patterns and breaks spatial locality in virtual addresses, rendering conventional address-based prefetchers ineffective in the context of CXL SSD. We identify evict correlation, where cache lines written back from the SSD's internal cache to flash within a short interval are likely to be re-referenced together by the host. By tracking data layout in flash pages and the SSD cache eviction history, this correlation can be detected, exploiting out-of-place updates and sub-page mapping in flash. Combined with a dynamic SSD cache allocation across tenants, our approach reconstructs access locality and reduces overall reference latency. Experiments on HPC and AI/ML workloads demonstrate accurate prefetching and efficient SSD resource utilization.