Nov 2026· IEEE transactions on computers· Vol 75, pp. 3899-3913· 0 citations· 38 references
Abstract
Persistent memory (PM) bridges the latency and cost gap between DRAM and SSDs. Within the DRAM–PM–SSD hierarchy, deploying key-value-separated key-value stores (KV-separated stores) is imperative for optimizing system longevity and performance. This architecture mitigates SSD write amplification and preserves PM endurance by minimizing writes. Existing KV-separated stores in the DRAM-SSD architecture, however, fail to fully exploit this three-tier hierarchy due to three issues. First, LSM-tree indexes incur high read amplification on PM. While learned indexes offer faster reads, they suffer from severe write-read asymmetry that can undermine overall efficiency in write-intensive workloads. Second, the lack of real-time obsolete data identification delays space reclamation. Third, contemporary KV stores treat PM as a passive write buffer, underutilizing its low read latency under skewed workloads. To address the above issues, we propose PALIKV – a PM-resident learned index-based KV store for the DRAM-PM-SSD hierarchy. We first design an adaptive two-level index that combines a PM learned index with a dynamic DRAM B+-tree buffer. This structure balances lookup efficiency with high write throughput while filtering redundant updates and extending PM lifespan. Second, the learned index enables real-time obsolete data identification. This facilitates an expedited garbage collection with device-specific reclamation granularity, thereby significantly reducing space amplification. Third, a hotness-aware data placement proactively migrates warm data from SSD to PM, allowing PM to serve skewed reads and eliminating the latency-constrained SSD from the critical read path. The experimental results unveil that PALIKV significantly outperforms SOTA KV-separated stores and DRAM-PM-SSD KV stores in terms of throughput and latency.
DuetKV is presented, a heterogeneous key-value store that treats NVM and SSD as peer foreground write engines and selects a destination for each request, and achieves up to 3.4 × the throughput of the strongest baseline on write-heavy workloads, while remaining competitive on read-heavy workloads.
Rui-Song Zhou, Liang Bao, Hai-Jun Zhang et al.· Proceedings of the Internati...· 0 citations
Zoned Namespace (ZNS) SSDs expose a sequential-write zone interface that reduces flash-level write amplification and offers cost and capacity advantages over conventional SSDs. Yet this interface creates a semantic mismatch for B+Tree-based storage engines, whose updates are fine-grained and logically in-place. Our wri...
Bo Chen, Jin-Lei Hu, Cheng-Xia Gong et al.· Proceedings of the Internati...· 0 citations
KV cache reuse accelerates LLM serving, but existing systems manage host DRAM and NVMe SSD as a tiered hierarchy where DRAM acts as an intermediate cache. Production LLM workloads break both premises of this hierarchy. First, bimodal reuse defeats DRAM temporal filtering, since workloads are dominated either by one-sho...
Xin Huang, Teng Ma, Zhuo-Ran Li et al.· 0 citations
Shingled Magnetic Recording (SMR) and Interlaced Magnetic Recording (IMR) technologies significantly increase disk storage density by overlapping internal tracks, but the resulting frequent read-modify-write(RMW) operations can cause severe performance jitter. Building Log-Structured Merge Tree (LSM-tree) based key-val...
Fang-Xing Yu, Zhi-Ke Li, Chi Zhang et al.· ACM Transactions on Architec...· 0 citations
Log-Structured Merge-Tree (LSM-tree) based Key-Value stores are foundational to data center storage but suffer from high tail latency due to a fundamental read-write trade-off and disruptive compaction. This paper introduces CmptQuiet, a system that breaks this trade-off to deliver low tail latency without sacrificing...
Jiu-Fei Liu, Kai-Yuan Xu, Shu Yin· Proceedings of the Internati...· 0 citations
LM-CXD bridges the semantic gap between the serving engine and the device, and exposes NAND-to-DRAM progress to the serving engine, and uses device DRAM as a GPU-accessible buffer to hide NAND latency under limited device DRAM.
Hyunsun Chung, Taewan Noh, Minji Kim et al.· 0 citations
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