Dependence of the capacitance of trap states at the oxide–semiconductor interface on the interface trap density in nanoscale silicon-on-insulator FinFET transistors and its effect on electrophysical parameters

Abstract

In this scientific research work, the dependence of the capacitance of trap states at the oxide–semiconductor inter - face ( C it ) on the interface trap density ( D it ) in nano-scale SOI FinFET transistors, as well as its effect on the main electrophysical parameters of the device, was systematically studied. The modeling was carried out on the basis of the drift–diffusion transport model, and quantum corrections based on the density gradient approach were applied to take into account quantum effects at the nanometer scale. The mobility model, the dependence on impurity atom concentration, and the velocity saturation effect occurring under strong electric fields were taken into consideration. The capacitance of trap states at the oxide–semiconductor interface was evaluated based on the relation C it = q²D it , and its effects on the electrostatic field potential, charge carrier concentration, the subthreshold slope (SS) of the current–voltage characteristic, threshold voltage ( V th ), and current–voltage characteristics were comprehensively analyzed. The results show that, with an increase in the interface trap density, an increase in C it is observed, which reduces the electrostatic control of the gate over the channel. As a consequence, the sensitivity of the electrostatic field potential to the gate voltage decreases, the charge carrier concentration along the channel decreases, and the subthreshold regime characteristics deteriorate. The obtained results show that the quality of the oxide–semiconductor interface in nano-scale SOI FinFET transistors is one of the main factors determining the operating characteristics of the device, and they justify the necessity of controlling surface states in the design of high-performance nanoelectronic devices.