Systematic Device-Level Design Exploration of Complementary Stacked Vertical-Channel Transistors (CVFETs) for Advanced Logic Applications

Abstract

This article presents a systematic device-level design exploration of complementary stacked vertical-channel transistors (CVFETs) and dual-channel CVFETs (dCVFETs). Key device factors are investigated, including source–drain asymmetry, nMOS/pMOS stacking order, terminal selection, electrode routing, and channel count. Their circuit-level impact is evaluated in terms of standard-cell area and energy–delay product (EDP). With the optimized device configuration, dual-sidewall routing reduces the average standard-cell area by 35.4% while maintaining EDP comparable to complementary field-effect transistors (CFETs). The dCVFET further reduces standard-cell EDP by 17.3% at the cost of a 9.3% area penalty. A 6T static random access memory (6T-SRAM) cell is also implemented using a novel dual-cut strategy, achieving a 37.8% area reduction and improved static noise margin compared with CFETs. These results show that device-level choices in CVFETs directly translate into logic benefits, providing design guidelines for future CVFET-based technologies.