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Xianyu Chen

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Open access Nov 2026

Systematic Device-Level Design Exploration of Complementary Stacked Vertical-Channel Transistors (CVFETs) for Advanced Logic Applications

This article presents a systematic device-level design exploration of complementary stacked vertical-channel transistors (CVFETs) and dual-channel CVFETs (dCVFETs). Key device factors are investigated, including source–drain asymmetry, nMOS/pMOS stacking order, terminal selection, electrode routing, and channel count....

Zhi-Cheng Wang, Yan-Tong Zheng, Tai-Ran Luo et al. · 0 citations

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