Systematic Device-Level Design Exploration of Complementary Stacked Vertical-Channel Transistors (CVFETs) for Advanced Logic Applications
This article presents a systematic device-level design exploration of complementary stacked vertical-channel transistors (CVFETs) and dual-channel CVFETs (dCVFETs). Key device factors are investigated, including source–drain asymmetry, nMOS/pMOS stacking order, terminal selection, electrode routing, and channel count....