Volume 5 Issue

Single-Ended 7T SRAM Cell Design Using 18 nm FinFET Technology for Low-Power and High-Stability Nanoscale VLSI Applications

This study presents the design and performance evaluation of a single-ended seven-transistor (7T) static random-access memory (SRAM) cell in 18 nm fin field-effect transistor (FinFET) technology for low-power, high-stability nanoscale very-large-scale integration (VLSI) applications. The cell combines separate read and...

Design and performance comparison of 6T, 8T and 11T SRAM cells using TSMC and UMC 65 nm CMOS technology

Systematic Device-Level Design Exploration of Complementary Stacked Vertical-Channel Transistors (CVFETs) for Advanced Logic Applications

This article presents a systematic device-level design exploration of complementary stacked vertical-channel transistors (CVFETs) and dual-channel CVFETs (dCVFETs). Key device factors are investigated, including source–drain asymmetry, nMOS/pMOS stacking order, terminal selection, electrode routing, and channel count....

Comparative Analysis and Genetic Algorithm Optimization of Multi-Transistor FinFET SRAM Topologies for SNM, Leakage, and Delay Improvement at 18nm

With continuous technology scaling, Static Random Access Memory (SRAM) faces significant challenges including increased leakage power, reduced stability, and higher delay. FinFET technology has emerged as a promising alternative to conventional CMOS technology due to its superior electrostatic control and reduced short...

Robust 12T-NVRH SRAM: Integrating STT-MTJ for Nonvolatility and Radiation-Induced Soft-Error Resilience in 28 nm CMOS

This work introduces a 12-transistor nonvolatile radiation-hardened (12T-NVRH) SRAM cell in 28 nm CMOS that integrates spin-transfer torque-magnetic tunnel junctions with a self-recovering latch to achieve simultaneous nonvolatility and multinode resilience.

An Ultra-Low-Power Imperfect Transmission Gate Flip-Flop for Near-Threshold Voltage Operation