Robust 12T-NVRH SRAM: Integrating STT-MTJ for Nonvolatility and Radiation-Induced Soft-Error Resilience in 28 nm CMOS
TL;DR
This work introduces a 12-transistor nonvolatile radiation-hardened (12T-NVRH) SRAM cell in 28 nm CMOS that integrates spin-transfer torque-magnetic tunnel junctions with a self-recovering latch to achieve simultaneous nonvolatility and multinode resilience.
Abstract
In modern nanoscale technologies, static random-access memory (SRAMs) are increasingly vulnerable to radiation-induced soft errors, including single event upsets (SEUs) and double node upsets (DNUs), due to reduced critical charge (<inline-formula><tex-math notation="LaTeX">$Q_{\text{crit}}$</tex-math></inline-formula>) and aggressive device scaling. At the same time, conventional SRAM suffers from volatility and considerable standby power loss. This work introduces a 12-transistor nonvolatile radiation-hardened (12T-NVRH) SRAM cell in 28 nm CMOS that integrates spin-transfer torque-magnetic tunnel junctions) with a self-recovering latch to achieve simultaneous nonvolatility and multinode resilience. The proposed design exhibits an SVNM of 485.7 mV, a WTV of 414.3 mV, and a <inline-formula><tex-math notation="LaTeX">$Q_{\text{crit}}$</tex-math></inline-formula> of 38.9 fC, yielding the highest power-quality metric among benchmarked architectures. Performance and reliability metrics are validated through extensive simulations in 28-nm UMC technology node.