Aug 2026· IEEE Transactions on Circuits and Systems Part 1: Regular Papers· Vol 73, pp. 5420-5433· 0 citations· 45 references
Computer Science
Abstract
Compute-in-Memory (CIM) based on resistive random access memory (RRAM) offers significant advantages in energy efficiency and parallelism, making it a promising solution for accelerating neural networks. However, the computational accuracy, energy efficiency, and flexibility of current CIM chips are still challenged by practical issues such as device and circuit-level non-ideality and the high overhead of peripheral circuits, which remain inadequately addressed in existing designs. To address these challenges, this work proposes REF-CIM, a 40nm robust, energy efficient and flexible RRAM- CIM macro that achieves non-ideality tolerance, high energy efficiency and configurable precision, featuring: 1) a complementary multi-bit input unit (CMIU) with symmetric bit-line access; 2) a proportional current-scaling clamp circuit (PCSC); 3) a distributed tree-based sparse analog-to-digital converter (DTS-ADC); and 4) a configurable multi-mode deployment scheme for supporting diverse neural network precisions. The performance of the proposed macro is evaluated through chip measurements, considering non-ideal effects such as IR-drop, device variation, and analog circuit noise. Simulation results calibrated with measurement data demonstrate a peak energy efficiency of 29.1 TOPS/W@8bIN/8bW/16bOUT, with classification accuracy reaching 92% on the CIFAR-10 dataset under 10% device variation.
Conventional computing architectures are reaching their scalability limits, while their energy demands increase rapidly. A bottleneck is the separation of memory and processing units, which requires a continuous data transfer. This memory wall increases the power consumption and limits the processing speed at the same time. Computing-in-Memory (CIM) has emerged as an alternative computing paradigm, where the data is processed directly within the memory array, thereby reducing data transfer costs. Emerging non-volatile devices such as magnetic-tunnel junctions (MTJ), phase-change memory (PCM), or resistive random-access memory (RRAM) are promising candidates for CIM. As re-programmable and highly scalable devices, they combine both computing and memory functionalities. While the feasibility of RRAM-based CIM has been proven, both in simulation and in experimental demonstrations, the operational reliability is still an ongoing issue. In this work, we demonstrate the parallel and cascading execution of logic functions in an RRAM-based CIM array. The experimental results are complemented by an in-depth simulation study to investigate the logic accuracy and optimization strategies. These results provide new insights into the reliability and logic correctness of resistive CIM and outline a potential path towards scalable and energy-efficient computing architectures.
L. Brackmann, Tobias Ziegler, N. Kopperberg et al.· npj Unconventional Computing· 0 citations
Analog computing-in-memory (ACIM) is a promising technology that performs computation on the bit lines to alleviate memory bottleneck, but the non-idealities at low operating voltages and high frequencies bottleneck overall energy efficiency (TOPS/W) and linearity. This work demonstrates that an ACIM macro in 22nm FDSOI can leverage independent back-gate biasing (VBB) to improve device characteristics, such as transconductance (gm), which enables a reduction in the operating voltage and power of peripheral circuits while simultaneously increasing operational speed. Circuit simulations show that targeted back-bias tuning reduces system RMSE by 50% (from 7% to 3.4%) or alternatively achieves a 20% increase in TOPS/W for VBB-optimized ACIM compared to unbiased operation. The study establishes the feasibility of utilizing back-gate biasing as a critical mechanism to achieve both high functional precision and high-speed operational flexibility in advanced FDSOI nodes.
Saideep Cherukuri, Apurba Prasad Padhy, N. V. Kidambi et al.· International Symposium on L...· 0 citations
Processing in memory (PIM) offers a compelling pathway to overcome the data movement bottleneck in modern AI and data-centric systems. This work introduces MITRA, a reconfigurable magnetic tunnel junction (MTJ)-based in-memory architecture that leverages stochastic computing (SC) to implement a broad class of transcendental and nonlinear functions directly within memory. By combining stochastic bit-stream processing with compact finite-state-machines (FSMs) embedded in MTJ-FinFET logic-in-memory structures, the proposed design achieves low-latency and power-efficient computation without external datapaths, unlike the binary counterparts. Circuit-level simulations in 14-nm FinFET technology verify correct state transitions, stable stochastic outputs, and predictable power profiles. Extensive evaluations demonstrate high accuracy even with short bit-streams. We further integrate the design into a neural-network classifier and develop an FSM-aware training strategy that compensates for approximation errors, achieving up to 96.9% classification accuracy on the UCI Optical Digit benchmark. Overall, MITRA provides a compact, reconfigurable platform for nonlinear processing in next-generation edge AI systems.
Farzad Razi, M. Moghadam, M. Najafi et al.· International Symposium on L...· 0 citations
A ring amplifier based switched-capacitor digital-toanalog converter (DAC) for charge-domain compute-in-memory (CIM) arrays is presented in a $65-\mathrm{nm}$ CMOS process. The proposed architecture employs a dual coarse/fine output stage with Monticelli and diode biasing, enabling fast slewing and stable operation across a wide data-dependent capacitive loads ranging from 50 to 500 fF, while using minimum-size transistors. The ringamp structure provides near rail-to-rail slewing with low quiescent current, improving energy efficiency for CIM workloads. Simulations show an average conversion energy of 140 fJ and a maximum operating frequency of 95 MHz. An energy figure-of-merit shows that the proposed DAC breaks the analytical energy lower-bound of the resistive DAC commonly used in charge-based CIMs, offering a 58% reduction in conversion energy in the average case, and a 20% reduction in the worst case.
Brian Rojkov, Shubham Ranjan, Sangmin Oh et al.· Midwest Symposium on Circuit...· 0 citations
Perpendicular Nanomagnetic Logic (pNML) has emerged as a promising beyond-CMOS computing technology due to its non-volatility, near-zero leakage power consumption, and capability for dense three-dimensional integration. However, the realization of scalable functional subsystems using field-clocked dipole-coupled nanomagnets remains a significant research challenge. This paper presents scalable implementations of Binary-to-Gray (B2G) and Gray-to-Binary (G2B) code converters using perpendicular nanomagnetic logic (pNML). The proposed architectures are realized using existing minority voter-based logic primitives and synthesized through the MagCAD nanomagnetic design framework, with functional validation performed via automatically generated VHDL models in the Xilinx Vivado environment. Complete physical-layout implementations are demonstrated for 3-bit, 4-bit, 8-bit, and 16-bit converter architectures. The results reveal a fundamental computational asymmetry between B2G and G2B conversion mechanisms. The B2G converters exhibit constant latency due to parallel XOR operations, achieving <inline-formula> <tex-math notation="LaTeX">$O(1)$ </tex-math></inline-formula> delay complexity, whereas G2B converters demonstrate linearly increasing delay with bit-width due to cascaded dependencies, resulting in <inline-formula> <tex-math notation="LaTeX">$O(N)$ </tex-math></inline-formula> complexity. This asymmetry is further reflected in the area–delay product (ADP), where B2G designs show moderate growth from 13.77 to <inline-formula> <tex-math notation="LaTeX">$92.92~\mu $ </tex-math></inline-formula>m<inline-formula> <tex-math notation="LaTeX">${}^{2}\cdot \mu $ </tex-math></inline-formula>s for 3-bit to 16-bit configurations, while G2B implementations exhibit a substantially larger increase from 30.84 to <inline-formula> <tex-math notation="LaTeX">$1349.42~\mu $ </tex-math></inline-formula>m<inline-formula> <tex-math notation="LaTeX">${}^{2}\cdot \mu $ </tex-math></inline-formula>s over the same range. The switching energy of CoFeB/MgO, Co/Pt, and DMI-enhanced Co/Pt/Ir nanomagnetic materials is found to scale with magnet count based on experimentally validated switching times. The switching power is determined by material switching time and arises from the cumulative switching of individual nanomagnets under field-clock excitation. When compared to the CoFeB baseline, the Co/Pt system reduces energy consumption by approximately 32%, while a Co/Pt/Ir multilayer system results in significant performance gains, achieving an average energy–delay product (EDP) improvement of approximately 82%. Furthermore, fabrication-variation analysis under ±5% and ±10% geometric perturbations confirms the robustness of the proposed architectures against practical manufacturing variations. The results indicate that pNML is a promising platform for low-power, non-volatile nanoscale computing and identify G2B conversion as the primary latency and efficiency bottleneck in scalable code conversion architectures.
N. Bathula, NEERAJ KUMAR MISRA· IEEE Access· 1 citation
This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.
Yang Chen, Daniele Storelli, Xin-Yi Zhao et al.· 0 citations
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