A Ringamp-Based DAC for Compute-in-Memory

Abstract

A ring amplifier based switched-capacitor digital-toanalog converter (DAC) for charge-domain compute-in-memory (CIM) arrays is presented in a $65-\mathrm{nm}$ CMOS process. The proposed architecture employs a dual coarse/fine output stage with Monticelli and diode biasing, enabling fast slewing and stable operation across a wide data-dependent capacitive loads ranging from 50 to 500 fF, while using minimum-size transistors. The ringamp structure provides near rail-to-rail slewing with low quiescent current, improving energy efficiency for CIM workloads. Simulations show an average conversion energy of 140 fJ and a maximum operating frequency of 95 MHz. An energy figure-of-merit shows that the proposed DAC breaks the analytical energy lower-bound of the resistive DAC commonly used in charge-based CIMs, offering a 58% reduction in conversion energy in the average case, and a 20% reduction in the worst case.