ULTRA-MACE: A Unified Low-Bit Trans-Precision Reconfigurable Multiply-Accumulate Compute Engine for Accelerated Computing
Abstract
The rising demand for energy- and resource-efficient edge-AI platforms calls for compute engines that balance throughput, flexibility, and run-time efficiency under tight bandwidth constraints. This brief presents ULTRA-MACE, a unified low-bit transprecision reconfigurable multiply-accumulate compute engine (MACE) that supports FP4 (E2M1), FP8 (E4M3), Posit-(8, 2), and Posit-(16, 3) through a six-stage vectorized pipeline with 128-bit quire accumulation. ULTRA-MACE employs a high-precision split mantissa multiplication scheme and an integrated gated bypass for ReLU, achieving <inline-formula> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula>/<inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula>/<inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula>/<inline-formula> <tex-math notation="LaTeX">$1\times $ </tex-math></inline-formula> throughput (FP4/FP8/Posit-8/Posit-16) without increasing bandwidth demand. Postroute results in 28 nm CMOS demonstrate a peak energy efficiency of 12.8 TFLOPS/W at 0.9 V and a compute density of 8.2 TFLOPS/mm<sup>2</sup>. Integrated into the TREA accelerator with 64 MACE, the FPGA prototype achieves 89% of theoretical peak performance and maintains practical accuracy with only 1.5% degradation relative to the FP32 baseline. Overall, these results demonstrate an efficient transprecision compute engine for edge-AI acceleration.
