A Low-Bit-First Multiprecision Processing Element for Energy-Efficient FPGA Implementation

Abstract

Multiprecision multiply-accumulate (MAC) units from INT2 to FP32 are increasingly needed on field-programmable gate arrays (FPGAs). However, the existing processing element (PE) designs mostly follow application-specific integrated circuit (ASIC)-oriented composition strategies. Their alignment and selection networks map to lookup table (LUT)-based multiplexing logic and incur rapidly increasing delay on FPGA platforms. We perform a controlled study of composition depth on three Xilinx platforms, spanning the Zynq-7000, Kintex UltraScale+, and Zynq UltraScale+ families. Each added composition layer incurs a steady frequency penalty, and four or more layers lose roughly half of the full-width maximum frequency. Based on this result, we propose hybrid high-precision composition (HHPC). The HHPC bounds in-array composition to a fixed depth. It moves residual high-precision assembly to postarray logic or inter-PE cooperation. It also preserves a fixed control structure across all modes. Based on HHPC, we implement a reconfigurable PE that supports INT2, INT4, INT8, FP16, and FP32 in a unified pipeline. FP32 is supported in two modes. A single PE produces one result every three cycles. A cooperative 3-PE tile sustains one FP32 MAC per cycle. On ZCU102, the proposed design achieves up to 310.60 GOPS/W for INT2 and 3.24 GFLOPS/W for FP32. It delivers up to $3.0\times $ higher energy efficiency than a comparable reconfigurable multiprecision PE with the same precision coverage.