A 64-bit high-precision flash computing-in-memory architecture with a parallel input scheme

Performance Analysis of In-Memory Computing Static Random Access Memory Array for Neural Network

Design, Stability Improvement, and Scaling of a 4-Transistor Static Latch for Digital Compute-in-Memory

This work presents a novel standard cell-compliant static latch that can be placed alongside digital logic and investigates the use of backgate biasing to improve system stability, and draws a comparison between the 22 nm implementations from the original work and the 12 nm implementation, indicating that moving to fin...

Robust Hybrid Computing-in-Memory System Based on 2T-2C and 4T-2C FRAM Cells

This paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array that provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption.

Precision-Reconfigurable Zero-Skipping SRAM Compute-in-Memory Architecture for Energy-Efficient Edge-AI Acceleration

This work proposes a Precision-Reconfigurable Zero-Skipping SRAM-CIM (PRZS-CIM) architecture that combines bit-serial exact multiply-accumulate decomposition, 4/6/8-bit precision control, row-level zero gating, and all-zero bit-plane suppression.

OctaPE: A Flexible PE Architecture for Multi-Dataflow Edge AI Acceleration

Deep Neural Network (DNN) accelerators based on systolic arrays have gained popularity as an efficient method of accelerating GEMM-intensive operations. However, because fixed dataflow a rchitectures and heterogeneous DNN workloads are incompatible, traditional systolic systems have low PE utilization. This work introd...

Multi-Operand In-Memory Computation Using Quad-Read 12T SRAM

In-memory computing (IMC) has emerged as a viable paradigm to overcome the limitations of the Von Neumann bottleneck, which limits frequent data transfer between memory and the CPU. Enabling two-operand Boolean and arithmetic operations within the SRAM array gives efficient data computing while multi-operand computatio...